Lines Matching +full:program +full:- +full:mem
9 The `Digilent Arty`_ is a line of FPGA-based development boards aimed for makers
11 different Xilinx FPGA (Spartan-7, Artix-7, or Zynq-7000 series).
13 Each board is equipped with on-board JTAG for FPGA programming and debugging,
17 .. figure:: arty_a7-35.jpg
19 :alt: Digilent Arty A7-35
21 Digilent Arty A7-35 (Credit: Digilent Inc)
23 The Spartan-7 and Artix-7 based Arty board do not contain a CPU, but require a
24 so-called soft processor to be instantiated within the FPGA in order to run
25 Zephyr. The Zynq-7000 based Arty boards are not yet supported by Zephyr.
27 ARM Cortex-M1/M3 DesignStart FPGA
32 both the Cortex-M1 and the Cortex-M3 reference designs. The Cortex-M1 design
33 targets either the Spartan-7 or Artix-7 based Arty boards, whereas the Cortex-M3
34 design only targets the Artix-7 based boards. Zephyr only supports the Artix-7
37 For more information about the ARM Cortex-M1/M3 DesignStart FPGA, see the
40 - `Technical Resources for DesignStart FPGA`_
41 - `Technical Resources for DesignStart FPGA on Xilinx`_
42 - `ARM DesignStart FPGA Xilinx FAQs`_
48 hardware features of the Cortex-M1 reference design:
50 +-----------+------------+-------------------------------------+
53 | NVIC | on-chip | nested vector interrupt controller |
54 +-----------+------------+-------------------------------------+
55 | SYSTICK | on-chip | systick |
56 +-----------+------------+-------------------------------------+
57 | GPIO | on-chip | gpio, non-interrupt |
58 +-----------+------------+-------------------------------------+
59 | UART | on-chip | serial port-polling; |
60 | | | serial port-interrupt |
61 +-----------+------------+-------------------------------------+
62 | QSPI | on-chip | QSPI flash |
63 +-----------+------------+-------------------------------------+
65 The default configuration for the Cortex-M1 can be found in the defconfig file:
69 supports the following hardware features of the Cortex-M3 reference design:
71 +-----------+------------+-------------------------------------+
74 | MPU | on-chip | Memory Protection Unit |
75 +-----------+------------+-------------------------------------+
77 The default configuration for the Cortex-M3 can be found in the defconfig file:
85 The Cortex-M1 reference design is configured to use the 100 MHz external
86 oscillator on the board as CPU system clock whereas the Cortex-M3 reference
93 console and is accessible through the on-board JTAG adapter via USB connector
99 Two different debug probes are needed in order to program the board; the
100 on-board Digilent JTAG connected to the FPGA, and an external Serial Wire Debug
101 (SWD) capable debug probe connected to the ARM Cortex-M1 CPU.
103 The on-board JTAG is used for configuring and debugging the Xilinx FPGA
114 using Xilinx Vivado as described in the ARM Cortex-M1/Cortex-M3 DesignStart FPGA
119 to use the :ref:`openocd-debug-host-tools`:
121 .. code-block:: console
123 openocd -f board/arty_s7.cfg -c "init;\
129 .. code-block:: console
131 openocd -f board/arty_s7.cfg -c "init;\
137 The pre-built FPGA bitstream only works for Arty boards equipped with an
138 Artix-35T FPGA. For other Arty variants (e.g. the Arty A7-100) the bitstream
147 The UART console is available via the on-board JTAG on USB connector
148 ``J10``. The on-board JTAG will enumerate as two USB serial ports. The UART is
154 - Speed: 115200
155 - Data: 8 bits
156 - Parity: None
157 - Stop bits: 1
162 Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application
163 for the Cortex-M1 reference design:
165 .. zephyr-app-commands::
166 :zephyr-app: samples/hello_world
172 .. code-block:: console
174 *** Booting Zephyr OS build zephyr-v2.3.99 ***
177 The same procedure can be used for the Cortex-M3 reference design.
185 the ARM Cortex-M1/M3 DesignStart FPGA Xilinx edition user guide. If the
188 dump :file:`zephyr.mem` file suitable for initialising the block RAM using
194 Here is an example for the :zephyr:code-sample:`hello_world` application.
196 .. zephyr-app-commands::
197 :zephyr-app: samples/hello_world
204 .. code-block:: console
206 *** Booting Zephyr OS build zephyr-v2.3.99 ***
213 https://www.arm.com/resources/designstart/designstart-fpga
216 https://developer.arm.com/ip-products/designstart/fpga
219 https://developer.arm.com/ip-products/designstart/fpga/fpga-xilinx
222 https://developer.arm.com/ip-products/designstart/fpga/fpga-xilinx-faqs
228 https://www.xilinx.com/products/design-tools/vivado.html