Lines Matching +full:connected +full:- +full:ground
9 a low-power 3-axis accelerometer and an on-board eSIM.
10 The development kit provides interfacing to the SoM through USB-C,
17 ARM Cortex-M33F CPU, ARMv8-M Security Extension and the
24 * :abbr:`I2C (Inter-Integrated Circuit)`
31 * :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)`
45 The detailed information about the on-board hardware can be found at the `Icarus SoM Product Websit…
53 +----+-------+------------------------------------+------------------+
54 | # | Label | Description | Device-tree node |
56 | 1 | NC | Not Connected | - |
57 +----+-------+------------------------------------+------------------+
58 | 2 | IOREF | I/O reference, connected to 3.3V | - |
59 +----+-------+------------------------------------+------------------+
60 | 3 | RST | Reset of the nRF9160 | - |
61 +----+-------+------------------------------------+------------------+
62 | 4 | 3.3V | 3.3V Power output | - |
63 +----+-------+------------------------------------+------------------+
64 | 5 | 4.4V | Power output between Vbat and 4.4V | - |
65 +----+-------+------------------------------------+------------------+
66 | 6 | GND | Ground pin | - |
67 +----+-------+------------------------------------+------------------+
68 | 7 | GND | Ground pin | - |
69 +----+-------+------------------------------------+------------------+
70 | 8 | VIN | Power input pin (4.35V to 10.5V) | - |
71 +----+-------+------------------------------------+------------------+
73 +----+-------+------------------------------------+------------------+
75 +----+-------+------------------------------------+------------------+
77 +----+-------+------------------------------------+------------------+
79 +----+-------+------------------------------------+------------------+
81 +----+-------+------------------------------------+------------------+
83 +----+-------+------------------------------------+------------------+
85 +----+-------+------------------------------------+------------------+
87 +----+-------+------------------------------------+------------------+
89 +----+-------+------------------------------------+------------------+
91 +----+-------+------------------------------------+------------------+
93 +----+-------+------------------------------------+------------------+
95 +----+-------+------------------------------------+------------------+
97 +----+-------+------------------------------------+------------------+
99 +----+-------+------------------------------------+------------------+
101 +----+-------+------------------------------------+------------------+
103 +----+-------+------------------------------------+------------------+
105 +----+-------+------------------------------------+------------------+
106 | 26 | P13 | nRF9160 P0.13 or NC (Jumper-dependent) | gpio0 |
107 +----+-------+------------------------------------+------------------+
108 | 27 | P14 | nRF9160 P0.14 or NC (Jumper-dependent) | gpio0 |
109 +----+-------+------------------------------------+------------------+
111 +----+-------+------------------------------------+------------------+
112 | 29 | GND | Ground pin | - |
113 +----+-------+------------------------------------+------------------+
114 | 30 | AREF | NC or AIN1 (Jumper-dependent) | gpio0 |
115 +----+-------+------------------------------------+------------------+
117 +----+-------+------------------------------------+------------------+
119 +----+-------+------------------------------------+------------------+
120 | - | TS | Pin for optional battery thermistor| - |
121 +----+-------+------------------------------------+------------------+
122 | - | CHG | Pin for battery charging indication| - |
123 +----+-------+------------------------------------+------------------+
124 | - | CE | Pin for enabling/disabling charging| - |
125 +----+-------+------------------------------------+------------------+
128 nRF9160 pins connected internally:
130 +--------------+------------------------------+---------------------+
131 | nRF9160 pin | Function | Device-tree node |
133 | P0.03 | Blue LED | led0 / pwm-led0 |
134 +--------------+------------------------------+---------------------+
136 +--------------+------------------------------+---------------------+
138 +--------------+------------------------------+---------------------+
139 | P0.23 | Connected to the user button | gpio0 / button0 |
140 +--------------+------------------------------+---------------------+
142 +--------------+------------------------------+---------------------+
143 | P0.28 | Accelerometer Interrupt 2 | lis2dh12-accel |
144 +--------------+------------------------------+---------------------+
145 | P0.29 | Accelerometer Interrupt 1 | lis2dh12-accel |
146 +--------------+------------------------------+---------------------+
154 +-----------+------------+----------------------+
157 | ADC | on-chip | adc |
158 +-----------+------------+----------------------+
159 | CLOCK | on-chip | clock_control |
160 +-----------+------------+----------------------+
161 | FLASH | on-chip | flash |
162 +-----------+------------+----------------------+
163 | GPIO | on-chip | gpio |
164 +-----------+------------+----------------------+
165 | I2C(M) | on-chip | i2c |
166 +-----------+------------+----------------------+
167 | MPU | on-chip | arch/arm |
168 +-----------+------------+----------------------+
169 | NVIC | on-chip | arch/arm |
170 +-----------+------------+----------------------+
171 | PWM | on-chip | pwm |
172 +-----------+------------+----------------------+
173 | SPI(M/S) | on-chip | spi |
174 +-----------+------------+----------------------+
175 | SPU | on-chip | system protection |
176 +-----------+------------+----------------------+
177 | UARTE | on-chip | serial |
178 +-----------+------------+----------------------+
180 +-----------+------------+----------------------+
185 The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting
191 - Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented
192 with the System Protection Unit and is used to define secure and non-secure
195 - Secure boot.
197 Building Secure/Non-Secure Zephyr applications
202 1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_som_dk``.
203 2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_som_dk/ns``.
209 When building a Secure/Non-Secure application, the Secure application will
210 have to set the IDAU (SPU) configuration to allow Non-Secure access to all
211 CPU resources utilized by the Non-Secure application firmware. SPU
212 configuration shall take place before jumping to the Non-Secure application.
220 .. target-notes::
223 https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau
226 https://www.actinius.com/icarus-som
229 https://www.actinius.com/icarus-som-dk
232 https://docs.actinius.com/icarus-som/introduction