104 #define XTENSA_MMU_L2_POS(vaddr) \  argument
105 	(((vaddr) & XTENSA_MMU_L2_MASK) >> 12U)
108 #define XTENSA_MMU_L1_POS(vaddr) \  argument
109 	((vaddr) >> 22U)
191 #define XTENSA_MMU_PTE_ENTRY_VADDR(base, vaddr) \  argument
192 	((base) + (((vaddr) / KB(4)) * 4))
401 	uint32_t vaddr;  in xtensa_dtlb_vaddr_read()  local
403 	__asm__ volatile("rdtlb0  %0, %1\n\t" : "=a" (vaddr) : "a" (entry));  in xtensa_dtlb_vaddr_read()
404 	return (void *)(vaddr & XTENSA_MMU_PTE_VPN_MASK);  in xtensa_dtlb_vaddr_read()
427 	uint32_t vaddr;  in xtensa_itlb_vaddr_read()  local
429 	__asm__ volatile("ritlb0  %0, %1\n\t" : "=a" (vaddr), "+a" (entry));  in xtensa_itlb_vaddr_read()
430 	return (void *)(vaddr & XTENSA_MMU_PTE_VPN_MASK);  in xtensa_itlb_vaddr_read()
453 static ALWAYS_INLINE uint32_t xtensa_itlb_probe(void *vaddr)  in xtensa_itlb_probe()  argument
457 	__asm__ __volatile__("pitlb  %0, %1\n\t" : "=a" (ret) : "a" ((uint32_t)vaddr));  in xtensa_itlb_probe()
468 static ALWAYS_INLINE uint32_t xtensa_dtlb_probe(void *vaddr)  in xtensa_dtlb_probe()  argument
472 	__asm__ __volatile__("pdtlb  %0, %1\n\t" : "=a" (ret) : "a" ((uint32_t)vaddr));  in xtensa_dtlb_probe()
484 static inline void xtensa_itlb_vaddr_invalidate(void *vaddr)  in xtensa_itlb_vaddr_invalidate()  argument
486 	uint32_t entry = xtensa_itlb_probe(vaddr);  in xtensa_itlb_vaddr_invalidate()
501 static inline void xtensa_dtlb_vaddr_invalidate(void *vaddr)  in xtensa_dtlb_vaddr_invalidate()  argument
503 	uint32_t entry = xtensa_dtlb_probe(vaddr);  in xtensa_dtlb_vaddr_invalidate()