99 #define XTENSA_MMU_PTE_ASID_GET(pte, rasid) \  argument
100 	(((rasid) >> ((((pte) & XTENSA_MMU_PTE_RING_MASK) \
199 #define XTENSA_MMU_RASID_ASID_GET(rasid, ring) \  argument
200 	(((rasid) >> ((ring) * 8)) & 0xff)
207 static ALWAYS_INLINE void xtensa_rasid_set(uint32_t rasid)  in xtensa_rasid_set()  argument
210 			"isync\n" : : "a"(rasid));  in xtensa_rasid_set()
220 	uint32_t rasid;  in xtensa_rasid_get()  local
222 	__asm__ volatile("rsr %0, rasid" : "=a"(rasid));  in xtensa_rasid_get()
223 	return rasid;  in xtensa_rasid_get()
234 	uint32_t rasid = xtensa_rasid_get();  in xtensa_rasid_asid_set()  local
236 	rasid = (rasid & ~(0xff << (ring * 8))) | ((uint32_t)asid << (ring * 8));  in xtensa_rasid_asid_set()
238 	xtensa_rasid_set(rasid);  in xtensa_rasid_asid_set()