47 /** Mask for ring in PTE */
50 /** Number of bits to shift for ring in PTE */
67 #define XTENSA_MMU_PTE(paddr, ring, sw, attr) \  argument
69 	 (((ring) << XTENSA_MMU_PTE_RING_SHIFT) & XTENSA_MMU_PTE_RING_MASK) | \
89 /** Set the ring in a PTE */
90 #define XTENSA_MMU_PTE_RING_SET(pte, ring) \  argument
92 	((ring) << XTENSA_MMU_PTE_RING_SHIFT))
94 /** Get the ring from a PTE */
98 /** Get the ASID from the RASID register corresponding to the ring in a PTE */
132 /** Kernel specific ASID. Ring field in the PTE */
135 /** User specific ASID. Ring field in the PTE */
138 /** Ring value for MMU_SHARED_ASID */
195  * Get ASID for a given ring from RASID register.
197  * RASID contains four 8-bit ASIDs, one per ring.
199 #define XTENSA_MMU_RASID_ASID_GET(rasid, ring) \  argument
200 	(((rasid) >> ((ring) * 8)) & 0xff)
227  * @brief Set a ring in RASID register to be particular value.
230  * @param ring ASID of which ring to be manipulated.
232 static ALWAYS_INLINE void xtensa_rasid_asid_set(uint8_t asid, uint8_t ring)  in xtensa_rasid_asid_set()  argument
236 	rasid = (rasid & ~(0xff << (ring * 8))) | ((uint32_t)asid << (ring * 8));  in xtensa_rasid_asid_set()