Lines Matching +full:level +full:- +full:detect

4  * SPDX-License-Identifier: Apache-2.0
27  * A0-A15) to their ABI-defined spill regions on the stack.
35  * and repeats until all but the A0-A3 registers of the original frame
39  * - Vastly smaller code size
41  * - More easily maintained if changes are needed to window over/underflow
44  * - Requires no scratch registers to do its work, so can be used safely in any
47  * - If the WOE bit is not enabled (for example, in code written for
50  * - In memory protection situations, this relies on the existing
57  * - Hilariously it's ACTUALLY FASTER than the HAL routine.  And not
59  *   file on an LX6 core (ESP-32) I'm measuring 145 cycles to spill
103  * area pointed to by the current stack pointer A1. The Floating-Point
295  *    (to save A0-A3) from registers.  But they find their
296  *    already-spilled callER's stack pointer (to save higher GPRs) from
312  * We make this work by inserting TWO 4-register frames between
318  * mode) OR the existing "post-context-save" stack pointer (when
320  * these are both only 4-registers, neither needs its own caller for
336  * pre-spill it with one stack pointer for the "lower" call to see and
351  * clobbered.  A4-A15 become part of called frames and MUST NOT BE IN
374 	 * running in a valid frame, so re-enable interrupts.
394  * the stack pointer decremented across a base save area, A0-A3 and
396  * level-specific C handler function.
401  * point to some kind of per-CPU record struct) and offsets within
435 	/* Setting the interrupt mask to the max non-debug level
437 	 * high level interrupts until processing of that lower level
449 	/* There's a gotcha with level 1 handlers: the INTLEVEL field
474 	 * resulting frames are invalid/non-reentrant, so we can't
526 	addi a0, a0, -1
590 /* Defines an exception/interrupt vector for a specified level.  Saves
591  * off the interrupted A0-A3 registers and the per-level PS/PC
595  * Arguments are a numeric interrupt level and symbol names for the
597  * particular level.
600  * no particularly good reason.  Only level 1 has any code generation
601  * difference, because it is the legacy exception level that predates
620 .pushsection .Level\LVL\()InterruptVector.text, "ax"
657 	 * keep ping-ponging between double and kernel/user exception
661 	 * the stashed DEPC value to detect if the next exception could
678 	addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF
683 	/* Level "1" is the exception handler, which uses a different
691 	/* TLB misses also come through level 1 interrupts.
695 	 * The interrupt mask will be cleared for non-TLB-misses
696 	 * level 1 interrupt later in the handler code.
724 	 * to put the literals into a per-vector section, then link
749 .pushsection .Level\LVL\()InterruptVector.text, "ax"