Lines Matching full:ps
30 * EXCM and WOE bit be enabled in PS, and relies on repeated hardware
164 * Does not populate or modify the PS/PC save locations.
346 * area) in A3. Exceptions should be enabled via PS.EXCM, but
347 * PS.INTLEVEL must (!) be set such that no nested interrupts can
379 wsr.ps a2
395 * PS/PC already spilled to the stack in the BSA, and A2 containing a
440 rsr.ps a0
445 wsr.ps a0
461 rsr.ps a0
465 rsr.ps a0
468 wsr.ps a0
478 * PS.INTLEVEL at maximum to mask all interrupts and stash the
490 wsr.ps a0
591 * off the interrupted A0-A3 registers and the per-level PS/PC
648 * another exception (through user/kernel if PS.EXCM is
649 * cleared, or through double if PS.EXCM is set). This can
651 * faults on Xtensa. Once PS.EXCM is set, it keeps going
653 * However, our exception code needs to unmask PS.EXCM to
656 * depending on PS.UM. If there is continuous faults, it may
685 * interrupted PS, instead we just assume that the CPU has
689 rsr.ps a0