Lines Matching +full:time +full:- +full:slot

4  * SPDX-License-Identifier: Apache-2.0
10 #include <xtensa/xtensa-types.h>
14 #include <xtensa/config/core-isa.h>
21  * SP-0 <-- Interrupted stack pointer points here
23  * SP-4   Caller A3 spill slot \
24  * SP-8   Caller A2 spill slot |
25  * SP-12  Caller A1 spill slot + (Part of ABI standard)
26  * SP-16  Caller A0 spill slot /
28  * SP-20  Saved A3
29  * SP-24  Saved A2
30  * SP-28  Unused (not "Saved A1" because the SP is saved externally as a handle)
31  * SP-32  Saved A0
33  * SP-36  Saved PC (address to jump to following restore)
34  * SP-40  Saved/interrupted PS special register
36  * SP-44  Saved SAR special register
38  * SP-48  Saved LBEG special register (if loops enabled)
39  * SP-52  Saved LEND special register (if loops enabled)
40  * SP-56  Saved LCOUNT special register (if loops enabled)
42  * SP-60  Saved SCOMPARE special register (if S32C1I enabled)
44  * SP-64  Saved EXCCAUSE special register
46  * SP-68  Saved THREADPTR special register (if processor has thread pointer)
48  *       (The above fixed-size region is known as the "base save area" in the
51  * - 18 FPU registers (if FPU is present and CONFIG_FPU_SHARING enabled)
53  * - Saved A7 \
54  * - Saved A6 |
55  * - Saved A5 +- If not in-use by another frame
56  * - Saved A4 /
58  * - Saved A11 \
59  * - Saved A10 |
60  * - Saved A9  +- If not in-use by another frame
61  * - Saved A8  /
63  * - Saved A15 \
64  * - Saved A14 |
65  * - Saved A13 +- If not in-use by another frame
66  * - Saved A12 /
68  * - Saved intermediate stack pointer (points to low word of base save
89  * Note that only A0-A3 are saved here. High registers
119 	 * manage alignment at run-time as we can not yet guarantee the
179  * Interrupt stack frame containing A0 - A15.
205  * Interrupt stack frame containing A0 - A11.
226  * Interrupt stack frame containing A0 - A7.
242  * Interrupt stack frame containing A0 - A3.