3  * SPDX-License-Identifier: Apache-2.0
8 #include <xtensa/config/core-isa.h>
37 	regs->rasid = (XTENSA_MMU_SHARED_ASID << 24) |  in compute_regs()
41 	regs->ptevaddr = CONFIG_XTENSA_MMU_PTEVADDR + user_asid * 0x400000;  in compute_regs()
44 	l1_page[XTENSA_MMU_L1_POS(regs->ptevaddr)] =  in compute_regs()
47 	regs->ptepin_at = (uint32_t)l1_page;  in compute_regs()
48 	regs->ptepin_as = XTENSA_MMU_PTE_ENTRY_VADDR(regs->ptevaddr, regs->ptevaddr)  in compute_regs()
61 	regs->vecpin_at = vb_pte;  in compute_regs()
62 	regs->vecpin_as = XTENSA_MMU_PTE_ENTRY_VADDR(regs->ptevaddr, vecbase)  in compute_regs()
87 	 * and is performance-sensitive.  in xtensa_set_paging()
93 	__asm__ volatile("j 1f\n"  in xtensa_set_paging()
94 			 ".align 16\n" /* enough for 5 insns */  in xtensa_set_paging()
95 			 "1:\n"  in xtensa_set_paging()
96 			 "wsr %0, PTEVADDR\n"  in xtensa_set_paging()
97 			 "wsr %1, RASID\n"  in xtensa_set_paging()
98 			 "wdtlb %2, %3\n"  in xtensa_set_paging()
99 			 "wdtlb %4, %5\n"  in xtensa_set_paging()
107  * but it also disables the hardware-initialized 512M TLB entries in
120  * might be double-mapped), so we invalidate that data TLB inside the
134 	 * For our initial implementation we just set the 4th slot (ring 3),  in xtensa_init_paging()
161 	__asm__ volatile("j z_xt_init_pc\n"  in xtensa_init_paging()
162 			 ".align 32\n" /* room for 10 insns */  in xtensa_init_paging()
163 			 ".globl z_xt_init_pc\n"  in xtensa_init_paging()
164 			 "z_xt_init_pc:\n"  in xtensa_init_paging()
165 			 "wsr %0, PTEVADDR\n"  in xtensa_init_paging()
166 			 "wsr %1, RASID\n"  in xtensa_init_paging()
167 			 "wdtlb %2, %3\n"  in xtensa_init_paging()
168 			 "wdtlb %4, %5\n"  in xtensa_init_paging()
169 			 "idtlb %6\n" /* invalidate pte */  in xtensa_init_paging()
170 			 "idtlb %7\n" /* invalidate stk */  in xtensa_init_paging()
171 			 "isync\n"  in xtensa_init_paging()
172 			 "iitlb %8\n" /* invalidate pc */  in xtensa_init_paging()
173 			 "isync\n" /* <--- traps a ITLB miss */  in xtensa_init_paging()