Lines Matching refs:will
17 support. A few are for bootstrap and initialization, and will be
36 non-kernel address space will get a separate ring 3 ASID set in RASID,
85 that is to just load the faulting PTE as an address, which will then
91 EXCM bit is set). This will produce a Double Exception fault, which
120 ensuring that a refill access will be able to find a PTE address.
157 care, as the CPU will throw an exception ("multi hit") if a memory
172 mapping condition, but it is safe as nothing will use it until we
176 exception handler into the data TLB. This will likewise not be
185 doing data accesses yet (including refills), and will resolve the
190 code page will then cause a TLB refill exception, which will work
196 reasonable hardware these regions will be near each other)
237 requires a TLB flush, and always will.
245 cacheable, then the hardware TLB refill process will be downstream of
249 the refill will be served from the data cache and not main memory.
260 mapped. Page table changes in the data cache of one CPU will be