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34 their ring field of the PTE that loaded them, via a simple translation
35 specified in the RASID special register. The intent is that each
37 such that you can switch between them without a TLB flush. The ASID
42 attribute value that can be used in a PTE).
57 This is extremely simple (just one extra hardware state that does just
64 physical address. Which means that the page tables occupy a 4M region
66 occupied by the running code. The 1024 pages in that range (not all
69 virtual memory. Note especially that exactly one of those pages
73 Obviously, the page table memory being virtual means that the fetch
78 already know we're missing that TLB entry), the hardware has exactly
83 The job of that exception handler is simply to ensure that the TLB has
85 that is to just load the faulting PTE as an address, which will then
99 turns out that the TLB entry doesn't permit the access requested, of
111 First, note that the refill process to load a PTE requires that the 4M
120 ensuring that a refill access will be able to find a PTE address.
122 But now note that the load from that PTE address for the refill is
124 requires doing a fetch via the instruction TLB. And that obviously
125 means that the page(s) containing the exception handler must never
137 the data TLB, such that instruction fetches always find their TLB
151 attributes specifying that they are accessible only to an ASID of 1
156 But that means that enabling page-level translation requires some
165 1. Ensure that the initialization routine does not cross a page
166 boundary (to prevent stray TLB refill exceptions), that it occupies
168 temporarily double-map), and that it operates entirely in registers
201 top of physical memory. The intent here would (presumably) be that
202 these would be used by the kernel for all physical memory and that the
213 intended to be used similarly. The intent of the design is that at
227 in virtual space, such that the page tables don't overlap. This is
234 Note, obviously, that any change of the mappings within an ASID
241 A final important note is that the hardware PTE refill fetch works
244 loaded. This means that if the page table entries are marked
253 of access variability. But it also means that the TLB entries end up
254 being stored twice in the same CPU, wasting transistors that could
257 But it is also important to note that the L1 data cache on Xtensa is
266 The result is that, when SMP is enabled, Zephyr must ensure that all