Lines Matching full:page
23 and data spaces, but the hardware page table refill mechanism (see
44 ## Virtually-mapped Page Tables
47 extremely confusing) "page table" format. The simplest was to begin
53 10 bits with the bottom two bits set to zero" (i.e. the page frame
59 memory fetch vs. e.g. the 2-5 fetches required to walk a page table on
64 physical address. Which means that the page tables occupy a 4M region
70 contains the 1024 PTE entries for the 4M page table itself, pointed to
73 Obviously, the page table memory being virtual means that the fetch
74 can fail: there are 1024 possible pages in a complete page table
77 page translation we want (NOT for the original requested address, we
84 an entry for the page table page we want. And the simplest way to do
88 within the 4M page table region. This is an typical/expected runtime
104 The page-tables-specified-in-virtual-memory trick works very well in
114 page of PTE entries (which itself lives in the 4M page table region!).
115 This page must always be in the TLB.
118 ways (ways 7-9) with at least one 4k page mapping each. We can use
119 one of these to "pin" the top-level page table entry in place,
125 means that the page(s) containing the exception handler must never
128 Ideally we would just pin the vector/handler page in the ITLB in the
135 vector page to succeed always. The way to do this is to similarly pin
136 the page table page containing the (single) PTE for the vector page in
145 execute code before the OS is able to initialize a refillable page
156 But that means that enabling page-level translation requires some
161 0. Start with a fully-initialized page table layout, including the
162 top-level "L1" page containing the mappings for the page table
165 1. Ensure that the initialization routine does not cross a page
167 a separate 4k page than the exception vectors (which we must
171 2. Pin the L1 page table PTE into the data TLB. This creates a double
175 3. Pin the page table page containing the PTE for the TLB miss
190 code page will then cause a TLB refill exception, which will work
192 (Pedantic note: if the vector page and the currently-executing page
205 page-level control over physical memory (e.g. .text/.rodata is cached
214 context switch time, you can simply change RADID and the page table
219 Unfortunately this runs afoul of the virtual mapping of the page
220 refill: data TLB entries storing the 4M page table mapping space are
221 stored at ASID 1 (ring 0), they can't change when the page tables
224 smaller than the 1024-page PTE array).
227 in virtual space, such that the page tables don't overlap. This is
232 the statically allocated array of L1 page table pages.
244 loaded. This means that if the page table entries are marked
246 the L1 data cache on the CPU. If the physical memory storing page
248 page mapped within the same cache line, or to change the tables) then
260 mapped. Page table changes in the data cache of one CPU will be
262 notifying another CPU of changes to page mappings beyond doing
267 page table mappings in the system are set uncached. The OS makes no