Lines Matching full:entries

14 4-way-set-associative bank of entries mapping 4k pages, and 3-6
21 entries.  Zephyr manages both as needed, but symmetrically.  The
33 Live TLB entries are tagged with an 8-bit "ASID" value derived from
68 1048576 4-byte PTE entries, each describing a mapping for 4k of
70 contains the 1024 PTE entries for the 4M page table itself, pointed to
76 entries mapping all of them.  If we are missing a TLB entry for the
112 space of PTE entries be resolvable by the TLB directly, without
114 page of PTE entries (which itself lives in the 4M page table region!).
133 Instead, we load ITLB entries for vector handlers via the refill
150 cover all of memory.  These 8 entries are initialized as valid, with
153 uncached.  So at boot the CPU relies on these TLB entries to provide a
183 5. Disable the initial/way6 data TLB entries first, by setting them to
220 refill: data TLB entries storing the 4M page table mapping space are
244 loaded.  This means that if the page table entries are marked
253 of access variability.  But it also means that the TLB entries end up