Lines Matching full:but
21 entries. Zephyr manages both as needed, but symmetrically. The
23 and data spaces, but the hardware page table refill mechanism (see
40 initialization, but this mechanism isn't accessible to OS code except
80 one each for instruction/data TLBs, but in Zephyr they operate
105 practice. But it does have a chicken/egg problem with the initial
122 But now note that the load from that PTE address for the refill is
129 same way we do for data, but somewhat inexplicably, Xtensa does not
156 But that means that enabling page-level translation requires some
172 mapping condition, but it is safe as nothing will use it until we
180 exceptions is now complete, but cannot be used until we resolve the
206 but .data is not on SMP, etc...). And in any case we don't have any
207 such hardware to experiment with. But with a little address
253 of access variability. But it also means that the TLB entries end up
257 But it is also important to note that the L1 data cache on Xtensa is