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40 #define MMU_PWT BITL(3) /** Page Write Through */
41 #define MMU_PCD BITL(4) /** Page Cache Disable */
44 #define MMU_PS BITL(7) /** Page Size (non PTE)*/
45 #define MMU_PAT BITL(7) /** Page Attribute (PTE) */
60 /* Page fault error code flags. See Chapter 4.7 of the Intel SDM vol. 3A. */
61 #define PF_P BIT(0) /* 0 Non-present page 1 Protection violation */
73 * Dump out page table entries for a particular virtual memory address
78 * @param ptables Page tables to walk
84 * Fetch the page table entry for a virtual memory address
88 * @param val Value stored in page table entry, with address and flags
89 * @param ptables Toplevel pointer to page tables
96 * Debug function for dumping out page tables
98 * Iterates through the entire linked set of page table structures,
115 * magenta - entry is child page table
118 * @param ptables Top-level pointer to the page tables, as programmed in CR3
124 /* Legacy function - set identity-mapped MMU stack guard page to RO in the
125 * kernel's page tables to prevent writes and generate an exception
139 /* Called from page fault handler. ptables here is the ptage tables for the
140 * faulting user thread and not the current set of page tables
154 * structure here or the CPU will triple fault. The incoming page tables must in z_x86_kpti_is_access_ok()
160 __ASSERT((phys & PTABLES_ALIGN) == 0U, "unaligned page tables"); in z_x86_kpti_is_access_ok()
169 * current set of page tables
182 /* Return the virtual address of the page tables installed in this CPU in CR3 */
188 /* Return cr2 value, which contains the page fault linear address.
190 * Used by page fault handling code.
203 /* Kernel's page table. This is in CR3 for all supervisor threads.
208 /* Get the page tables used by this thread during normal execution */
215 * the kernel's page tables and not the page tables associated in z_x86_thread_page_tables_get()