Lines Matching refs:OUT
21 #define OUT(reg, val) sys_out8(val, reg + DT_REG_ADDR(DT_CHOSEN(zephyr_console))) macro
29 #define OUT(reg, val) sys_write32((val) & 0xff, mmio + (reg) * 4) macro
41 #define OUT(reg, val) sys_write8(val, BASE + reg) macro
74 OUT(REG_THR, c); in serout()
105 OUT(REG_IER, IER_DISABLE); /* Disable interrupts */ in z_x86_early_serial_init()
106 OUT(REG_LCR, LCR_DLAB_SELECT); /* DLAB select */ in z_x86_early_serial_init()
107 OUT(REG_BRDL, 1); /* Baud divisor = 1 */ in z_x86_early_serial_init()
108 OUT(REG_BRDH, 0); in z_x86_early_serial_init()
109 OUT(REG_LCR, LCR_8N1); /* LCR = 8n1 + DLAB off */ in z_x86_early_serial_init()
110 OUT(REG_MCR, MCR_DTR | MCR_RTS); in z_x86_early_serial_init()
113 OUT(REG_FCR, FCR_FIFO | FCR_FIFO_1 | FCR_RCVRCLR | FCR_XMITCLR); in z_x86_early_serial_init()