Lines Matching +full:start +full:- +full:line

2  * Copyright (c) 2013-2014 Wind River Systems, Inc.
5  * SPDX-License-Identifier: Apache-2.0
21 /* Not Write-through bit */
35 	/* Enable write-back caching by clearing the NW and CD bits */  in arch_dcache_enable()
47 	/* Enter the no-fill mode by setting NW=0 and CD=1 */  in arch_dcache_disable()
83  * sys_cache_flush() iterates on the cache lines, a cache line alignment for
86  * The cache line size is specified via the d-cache-line-size DTS property.
91 	uintptr_t start = (uintptr_t)start_addr;  in arch_dcache_flush_range()  local
92 	uintptr_t end = start + size;  in arch_dcache_flush_range()
95 		return -ENOTSUP;  in arch_dcache_flush_range()
100 	for (; start < end; start += line_size) {  in arch_dcache_flush_range()
102 				"+m"(*(volatile char *)start));  in arch_dcache_flush_range()
108 	__asm__ volatile("lock; addl $0,-4(%%esp);\n\t":::"memory", "cc");  in arch_dcache_flush_range()