Lines Matching refs:t0
27 RV_E( op t0, __struct_arch_esf_t0_OFFSET(sp) );\
144 sr t0, _curr_cpu_arch_user_exc_tmp0(s0)
148 csrr t0, mstatus
150 and t0, t0, t1
151 bnez t0, 1f
154 mv t0, sp
160 sr t0, (-__struct_arch_esf_SIZEOF + __struct_arch_esf_sp_OFFSET)(sp)
163 lr t0, ___cpu_t_current_OFFSET(s0)
164 lr tp, _thread_offset_to_tls(t0)
177 lui t0, %tprel_hi(is_user_mode)
178 add t0, t0, tp, %tprel_add(is_user_mode)
179 sb zero, %tprel_lo(is_user_mode)(t0)
182 lr t0, _curr_cpu_arch_user_exc_tmp0(s0)
202 csrr t0, mepc
203 sr t0, __struct_arch_esf_mepc_OFFSET(sp)
228 lw t2, 0(t0) /* t0 = mepc */
231 andi t0, t2, 0x7f /* keep only the opcode bits */
242 xori t1, t0, 0b1010011 /* OP-FP */
244 ori t1, t0, 0b0100000
247 ori t1, t0, 0b0001100
259 xori t1, t0, 0b1110011 /* SYSTEM opcode */
261 srli t0, t2, 12
262 andi t0, t0, 0x3
263 beqz t0, 2f /* not a CSR insn */
264 srli t0, t2, 20 /* isolate the csr register number */
265 beqz t0, 2f /* 0=ustatus */
266 andi t0, t0, ~0x3 /* 1=fflags, 2=frm, 3=fcsr */
268 bnez t0, no_fp
270 beqz t0, is_fp
286 srli t0, t2, 8
288 andi t1, t0, 0b01100000
292 andi t1, t0, 0b00100000
303 lr t0, ___cpu_t_current_OFFSET(s0)
304 lb t1, _thread_offset_to_exception_depth(t0)
306 sb t1, _thread_offset_to_exception_depth(t0)
332 csrr t0, mcause
333 srli t0, t0, RISCV_MCAUSE_IRQ_POS
334 bnez t0, is_interrupt
342 csrr t0, mcause
344 and t0, t0, t2
351 beq t0, t1, is_kernel_syscall
359 beq t0, t1, is_user_syscall
366 csrr t0, mstatus
368 and t0, t0, t1
369 bnez t0, 1f
398 lr t0, __struct_arch_esf_mepc_OFFSET(sp)
399 addi t0, t0, 4
400 sr t0, __struct_arch_esf_mepc_OFFSET(sp)
411 lr t0, __struct_arch_esf_t0_OFFSET(sp)
414 beqz t0, do_fault
418 beq t0, t1, do_irq_offload
423 bne t0, t1, skip_schedule
496 mv t0, sp
501 sr t0, 0(sp)
540 lr t0, __struct_arch_esf_t0_OFFSET(sp)
552 bltu t0, t1, valid_syscall_id
555 mv a0, t0
556 li t0, K_SYSCALL_BAD
562 slli t1, t0, RV_REGSHIFT # Determine offset from indice value
589 lr t0, __struct_arch_esf_mstatus_OFFSET(sp)
591 and t0, t0, t1
592 bnez t0, 1f
612 mv t0, sp
620 sr t0, 0(sp)
634 li t0, CONFIG_RISCV_MCAUSE_EXCEPTION_MASK
635 and a0, a0, t0
647 la t0, _sw_isr_table
649 add t0, t0, a0
652 lr a0, 0(t0)
655 lr t1, RV_REGSIZE(t0)
730 lr t0, ___cpu_t_current_OFFSET(s0)
731 lb t1, _thread_offset_to_exception_depth(t0)
733 sb t1, _thread_offset_to_exception_depth(t0)
738 lr t0, __struct_arch_esf_mepc_OFFSET(sp)
740 csrw mepc, t0
750 and t0, t2, t1
751 bnez t0, 1f
761 lui t0, %tprel_hi(is_user_mode)
762 add t0, t0, tp, %tprel_add(is_user_mode)
763 sb t1, %tprel_lo(is_user_mode)(t0)
766 add t0, sp, __struct_arch_esf_SIZEOF
767 sr t0, _curr_cpu_arch_user_exc_sp(s0)
775 addi t0, sp, __struct_arch_esf_SIZEOF
776 sr t0, __struct_arch_esf_sp_OFFSET(sp)