Lines Matching +full:op +full:- +full:mode
2 * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
6 * SPDX-License-Identifier: Apache-2.0
26 #define DO_CALLER_SAVED(op) \ argument
27 RV_E( op t0, __struct_arch_esf_t0_OFFSET(sp) );\
28 RV_E( op t1, __struct_arch_esf_t1_OFFSET(sp) );\
29 RV_E( op t2, __struct_arch_esf_t2_OFFSET(sp) );\
30 RV_I( op t3, __struct_arch_esf_t3_OFFSET(sp) );\
31 RV_I( op t4, __struct_arch_esf_t4_OFFSET(sp) );\
32 RV_I( op t5, __struct_arch_esf_t5_OFFSET(sp) );\
33 RV_I( op t6, __struct_arch_esf_t6_OFFSET(sp) );\
34 RV_E( op a0, __struct_arch_esf_a0_OFFSET(sp) );\
35 RV_E( op a1, __struct_arch_esf_a1_OFFSET(sp) );\
36 RV_E( op a2, __struct_arch_esf_a2_OFFSET(sp) );\
37 RV_E( op a3, __struct_arch_esf_a3_OFFSET(sp) );\
38 RV_E( op a4, __struct_arch_esf_a4_OFFSET(sp) );\
39 RV_E( op a5, __struct_arch_esf_a5_OFFSET(sp) );\
40 RV_I( op a6, __struct_arch_esf_a6_OFFSET(sp) );\
41 RV_I( op a7, __struct_arch_esf_a7_OFFSET(sp) );\
42 RV_E( op ra, __struct_arch_esf_ra_OFFSET(sp) )
45 /* Convenience macro for storing callee saved register [s0 - s11] states. */
110 * Generic architecture-level IRQ handling, along with callouts to
111 * SoC-specific routines.
117 * Since RISC-V does not completely prescribe IRQ handling behavior,
122 * - __soc_is_irq (optional): decide if we're handling an interrupt or an
124 * - __soc_handle_irq: handle SoC-specific details for a pending IRQ
125 * (e.g. clear a pending bit in a SoC-specific register)
127 * If CONFIG_RISCV_SOC_CONTEXT_SAVE=y, calls to SoC-level context save/restore
160 sr t0, (-__struct_arch_esf_SIZEOF + __struct_arch_esf_sp_OFFSET)(sp)
176 /* Clear our per-thread usermode flag */
192 /* Save caller-saved registers on current thread stack. */
193 addi sp, sp, -__struct_arch_esf_SIZEOF
234 * 0000111 = LOAD-FP
235 * 0100111 = STORE-FP
240 * 1010011 = OP-FP
242 xori t1, t0, 0b1010011 /* OP-FP */
245 xori t1, t1, 0b0100111 /* LOAD-FP / STORE-FP */
255 * CSR format: csr#[31-20] src[19-15] op[14-12] dst[11-7] SYSTEM[6-0]
256 * SYSTEM = 0b1110011, op = 0b.xx where xx is never 0
302 no_fp: /* increment arch_current_thread()->arch.exception_depth */
308 /* configure the FPU for exception mode */
320 * (SOC dependent). Following the RISC-V architecture spec, the MSB
323 * SOCs (like pulpino or riscv-qemu), the MSB is never set to indicate
339 * perform a context-switch or an IRQ offload. Otherwise call _Fault
356 * for user mode thread.
364 * kernel mode stack guard.
403 /* Re-activate PMP for m-mode */
429 * When an ECALL is used for a context-switch, the current thread has
434 add t1, t1, -1
462 /* Allocate space for caller-saved registers on current thread stack */
463 addi sp, sp, -__callee_saved_t_SIZEOF
465 /* Save callee-saved registers to be passed as 3rd arg */
489 /* Increment _current_cpu->nested */
500 addi sp, sp, -16
516 * PMP for kernel mode stack guard.
522 /* It is safe to re-enable IRQs now */
543 addi sp, sp, -4
587 * PMP for kernel mode stack guard.
597 1: /* Re-activate PMP for m-mode */
605 /* Increment _current_cpu->nested */
617 * In RISC-V, stack pointer needs to be 16-byte aligned
619 addi sp, sp, -16
645 * (table is 2-word wide, we should shift index accordingly)
667 /* Decrement _current_cpu->nested */
669 addi t2, t2, -1
692 addi sp, sp, -16
725 /* FPU handling upon exception mode exit */
729 /* decrement arch_current_thread()->arch.exception_depth */
732 add t1, t1, -1
745 * Check if we are returning to user mode. If so then we must
746 * set is_user_mode to true and preserve our kernel mode stack for
754 /* Remove kernel stack guard and Reconfigure PMP for user mode */
759 /* Set our per-thread usermode flag */
772 * We are returning to kernel mode. Store the stack pointer to
773 * be re-loaded further down.
786 /* Restore caller-saved registers from thread stack */