Lines Matching +full:invert +full:- +full:y

2 # SPDX-License-Identifier: Apache-2.0
7 	  RV32I Base Integer Instruction Set - 32bit
12 	  RV32E Base Integer Instruction Set (Embedded) - 32bit
16 	default y if 64BIT
18 	  RV64I Base Integer Instruction Set - 64bit
23 	  RV128I Base Integer Instruction Set - 128bit
28 	  (M) - Standard Extension for Integer Multiplication and Division
39 	  (A) - Standard Extension for Atomic Instructions
43 	  read-modify-write memory to support synchronization between multiple
44 	  RISC-V threads running in the same memory space.
49 	  (F) - Standard Extension for Single-Precision Floating-Point
51 	  Standard instruction-set extension for single-precision
52 	  floating-point, which is named "F" and adds single-precision
53 	  floating-point computational instructions compliant with the IEEE
54 	  754-2008 arithmetic standard.
60 	  (D) - Standard Extension for Double-Precision Floating-Point
62 	  Standard double-precision floating-point instruction-set extension,
63 	  which is named "D" and adds double-precision floating-point
64 	  computational instructions compliant with the IEEE 754-2008
84 	  (Q) - Standard Extension for Quad-Precision Floating-Point
86 	  Standard extension for 128-bit binary floating-point instructions
87 	  compliant with the IEEE 754-2008 arithmetic standard. The 128-bit or
88 	  quad-precision binary floatingpoint instruction subset is named "Q".
93 	  (C) - Standard Extension for Compressed Instructions
95 	  RISC-V standard compressed instruction set extension, named "C",
96 	  which reduces static and dynamic code size by adding short 16-bit
102 	  (Zicsr) - Standard Extension for Control and Status Register (CSR) Instructions
110 	  (Zifencei) - Standard Extension for Instruction-Fetch Fence
119 	  (Zaamo) - Atomic memory operation subset of the A extension
121 	  The Zaamo extension enables support for AMO*.W/D-style instructions.
126 	  (Zlrsc) - Load-Reserved/Store-Conditional subset of the A extension
128 	  The Zlrsc extension enables support for LR.W/D and SC.W/D-style instructions.
133 	  (Zba) - Zba BitManip Extension
137 	  doubleword) using both unsigned word-sized and XLEN-sized indices: a
143 	  (Zbb) - Zbb BitManip Extension (Basic bit-manipulation)
145 	  The Zbb instructions can be used for basic bit-manipulation (logical
152 	  (Zbc) - Zbc BitManip Extension (Carry-less multiplication)
154 	  The Zbc instructions can be used for carry-less multiplication that
160 	  (Zbs) - Zbs BitManip Extension (Single-bit instructions)
162 	  The Zbs instructions can be used for single-bit instructions that
163 	  provide a mechanism to set, clear, invert, or extract a single bit in