101 	/* search all CPUs for the owner we want */  in flush_owned_fpu()
108 		/* we found it live on CPU i */  in flush_owned_fpu()
120 			 * we would be stuck here.  in flush_owned_fpu()
123 			 * CPU, then we preemptively flush any live context  in flush_owned_fpu()
124 			 * on this CPU as well since we're likely to  in flush_owned_fpu()
156  * FPU access is disabled and we're trapped while in exception context.
158  * just to let the corresponding STR instructions execute, we simply
166 	 * We know there is no saved FPU context to check nor any  in simulate_str_q_insn()
181 		 * We're looking for STR (immediate, SIMD&FP) of the form:  in simulate_str_q_insn()
200 	/* did we do something? */  in simulate_str_q_insn()
216  * We also get here when FP regs are used while in exception as FP access
217  * is always disabled by default in that case. If so we save the FPU content
220  * there is nothing to save/restore for that context... as long as we
221  * don't get interrupted that is. To ensure that we mask interrupts to
249 		 * We were already in exception when the FPU access trap.  in z_arm64_fpu_trap()
250 		 * We give it access and prevent any further IRQ recursion  in z_arm64_fpu_trap()
251 		 * by disabling IRQs as we wouldn't be able to preserve the  in z_arm64_fpu_trap()
260 	 * Make sure the FPU context we need isn't live on another CPU.  in z_arm64_fpu_trap()
289 		/* We're about to execute non-exception code */  in fpu_access_update()
300 		 * access as we want to make sure IRQs are disabled before  in fpu_access_update()
319  * only if exception level is 0. If we switch to a thread that is still in