5  * SPDX-License-Identifier: Apache-2.0
31 static void DBG(char *msg, struct k_thread *th)  in DBG()  argument
37 	buf[3] = '0' + _current_cpu->id;  in DBG()
39 	strcat(buf, _current->name);  in DBG()
43 	strcat(buf, th->name);  in DBG()
46 	v = *(unsigned char *)&th->arch.saved_fp_context;  in DBG()
49 	*p++ = ((v >> 4) < 10) ? ((v >> 4) + '0') : ((v >> 4) - 10 + 'a');  in DBG()
50 	*p++ = ((v & 15) < 10) ? ((v & 15) + '0') : ((v & 15) - 10 + 'a');  in DBG()
51 	*p++ = '\n';  in DBG()
54 	k_str_out(buf, p - buf);  in DBG()
71 	struct k_thread *owner = atomic_ptr_get(&_current_cpu->arch.fpu_owner);  in arch_flush_local_fpu()
81 		z_arm64_fpu_save(&owner->arch.saved_fp_context);  in arch_flush_local_fpu()
85 		atomic_ptr_clear(&_current_cpu->arch.fpu_owner);  in arch_flush_local_fpu()
109 		if (i == _current_cpu->id) {  in flush_owned_fpu()
173 	uint32_t *pc = (uint32_t *)esf->elr;  in simulate_str_q_insn()
183 		 *  STR Q<n>, [SP, #<pimm>]  in simulate_str_q_insn()
185 		 * where 0 <= <n> <= 7 and <pimm> is a 12-bits multiple of 16.  in simulate_str_q_insn()
201 	if (pc != (uint32_t *)esf->elr) {  in simulate_str_q_insn()
203 		esf->elr = (uintptr_t)pc;  in simulate_str_q_insn()
238 	struct k_thread *owner = atomic_ptr_get(&_current_cpu->arch.fpu_owner);  in z_arm64_fpu_trap()
241 		z_arm64_fpu_save(&owner->arch.saved_fp_context);  in z_arm64_fpu_trap()
243 		atomic_ptr_clear(&_current_cpu->arch.fpu_owner);  in z_arm64_fpu_trap()
254 		esf->spsr |= DAIF_IRQ_BIT;  in z_arm64_fpu_trap()
267 	atomic_ptr_set(&_current_cpu->arch.fpu_owner, _current);  in z_arm64_fpu_trap()
270 	z_arm64_fpu_restore(&_current->arch.saved_fp_context);  in z_arm64_fpu_trap()
289 		/* We're about to execute non-exception code */  in fpu_access_update()
290 		if (atomic_ptr_get(&_current_cpu->arch.fpu_owner) == _current) {  in fpu_access_update()
320  * some exception context then FPU access would be re-evaluated at exception
336 		if (thread == atomic_ptr_get(&_current_cpu->arch.fpu_owner)) {  in arch_float_disable()