Lines Matching +full:extra +full:- +full:byte
4 # SPDX-License-Identifier: Apache-2.0
29 This option signifies the use of a CPU of the Cortex-M family.
44 This option signifies the use of a CPU of the Cortex-R family.
63 # GDB on ARM needs the extra registers
66 This option signifies the use of a CPU of the Cortex-A family.
69 # GDB for ARM expects up to 18 4-byte plus 8 12-byte
70 # registers - 336 HEX letters
76 From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
78 Thumb-2 technology is the instruction set underlying the ARM Cortex
83 Thumb-2 technology builds on the success of Thumb, the innovative
93 For performance optimized code Thumb-2 technology uses 31 percent
96 to prolong battery-life or to enrich the product feature set. Thumb-2
98 architecture-based processors.
103 …From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets
105 A32 instructions, known as Arm instructions in pre-Armv8 architectures,
106 are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions
107 are supported by both A-profile and R-profile architectures.
111 processor start-up. Much of its functionality was subsumed into T32 with
112 the introduction of Thumb-2 technology.
122 When only the Thumb-2 ISA is supported (i.e. on Cortex-M cores), the
123 assembler must use the Thumb-2 instruction set.
125 When both the Thumb-2 and ARM ISAs are supported (i.e. on Cortex-A
126 and Cortex-R cores), the assembler must use the ARM instruction set
131 bool "Compile C/C++ functions using Thumb-2 instruction set"
136 using the Thumb-2 instruction set.
142 When an additional natively-compiled language support is added
143 in the future, this symbol shall also specify the Thumb-2
150 bool "Align stacks on double-words (8 octets)"
155 of stack upon exception entry on Cortex-M3 and Cortex-M4 (ARMv7-M).
156 Note that for ARMv6-M, ARMv8-M, and Cortex-M7 MCUs stack alignment
193 bool "Thread Stack Guards based on built-in ARM stack limit checking"
197 Enable Thread/Interrupt Stack Guards via built-in Stack Pointer
207 - The built-in Stack Pointer limit checking, or
208 - the MPU-based stack guard
212 selection of the built-in Stack Pointer limit checking is
213 prioritized over the MPU-based stack guard. The developer
214 still has the option to manually select the MPU-based
224 applicable to ARMv8-M MCUs that implement the Security Extension.
228 execute only in Non-secure state.
231 and Non-Secure resources of the Cortex-M MCU.
233 Code executing in Non-Secure state may trigger Secure Faults,
234 if Secure MCU resources are accessed from the Non-Secure state.
245 is intended to execute in Non-Secure state. Execution of this
247 state. The option is only applicable to ARMv8-M MCUs that
251 Non-Secure state only, as well as to exclude code that is
254 Code executing in Non-Secure state has no access to Secure
255 resources of the Cortex-M MCU, and, therefore, it shall avoid
265 threads many not be context-switched-out while doing a Secure
285 point instructions are generated and uses FPU-specific calling
292 point instructions are generated but soft-float calling conventions.
297 bool "Half-precision floating point support"
300 This option enables the half-precision (16-bit) floating point support
302 `_Float16` (defined by ISO/IEC TS 18661-3:2015) types.
312 This option selects the IEEE 754-2008 format for FP16. This format can
313 represent normalized values in the range of 2^(-14) to 65504. There are
320 representation is similar to the IEEE 754-2008 format, but does not
323 2^(-14) to 131008.