Lines Matching +full:location +full:- +full:swo

3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
21 	  non-GIC or NVIC) interrupt controller.
23 	  A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
27 	  the Cortex-M ARM Nested Vectored Interrupt Controller (NVIC).
33 	  N.B. Since all Cortex-M cores have a NVIC, if this option is selected it
41 	  Relocates the rom_start region containing the boot-vector data and
45 	  This is useful for the Linux Remoteproc framework that uses the elf-loader
46 	  such that it is able to load the correct boot-vector (contained in rom_start)
47 	  into the correct memory location independent of the chosen zephyr,flash
50 	  Most SOCs include an alias for the boot-vector at address 0x00000000
55 	  is not placed into the boot-vector memory area.
63 		for code location. But the boot-vector must be placed into OCRAM_S for the
64 		CORTEX-M to boot (alias 0, real 0x00180000/32K available).
76 		  to the right memory region of the boot-vector.
79 		  -IMX7D the boot-vector is OCRAM_S (0x00180000, aliased at 0x0).
80 		  -IMX6SX the boot-vector is TCML (0x007F8000, aliased at 0x0).
81 		  -IMX8MQ the boot-vector is TCML (0x007E0000, aliased at 0x0).
82 		  -IMX8MN the boot-vector is ITCM (0x007E0000, aliased at 0x0).
97 		  Example for IMX7D that needs the boot-vector into OCRAM_S (0x00180000):
134 	  Enables a possibility to inject SoC-specific code just after WFI/WFE
184 	  MCU implements the nRF (vendor-specific) Security Attribution Unit.
185 	  (IDAU: "Implementation-Defined Attribution Unit", in accordance with
191 	  When enabled, indicates that SoC has an SWO output