Lines Matching +full:secure +full:- +full:only

4 # SPDX-License-Identifier: Apache-2.0
38 	  v2 ISA for the ARC-HS & ARC-EM cores
66 	  If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision
67 	  floating-point extension
73 	  If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision
74 	  floating-point and double assist instructions
135 	  - LPcc instruction
136 	  - LP_COUNT core reg
137 	  - LP_START, LP_END aux regs
144 	  Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1.
153 	  Interrupts available will be 0 to NUM_IRQS-1.
170 	  If fast interrupts are supported but there is only 1
174 	  to use second register bank - otherwise all interrupts will use
190 	  NOTE: we don't allow the configuration with FIRQ enabled and only one
239 	  - The ARC stack checking, or
240 	  - the MPU-based stack guard
245 	  prioritized over the MPU-based stack guard.
252 	  ARC EM cores w/o secure shield 2+2 mode support might be configured
262 	  RGF_NUM_BANKS the parameter is disabled by-default because banks syncronization
289 	  Depending on the configuration, CPU can contain accumulator reg-pair
299 	  This option is enabled when ARC core supports secure mode
306 	  The size of sjli (Secure Jump and Link Indexed) table. The
307 	  code in normal mode call secure services in secure mode through
311 	bool "Generate Secure Firmware"
316 	  is intended to execute in secure mode. The option is only
320 	  secure mode, as well as to exclude code that is designed to
321 	  execute only in normal mode.
323 	  Code executing in secure mode has access to both the secure
334 	  image is triggered by secure firmware that executes in secure
335 	  mode. The option is only applicable to ARC processors that
339 	  normal mode only, as well as to exclude code that is
340 	  designed to execute only in secure mode.
342 	  Code executing in normal mode has no access to secure
386 	bool "Make early stage SoC-specific initialization"
388 	  Call SoC per-core setup code on early stage initialization