Lines Matching +full:aux +full:- +full:reg

4 # SPDX-License-Identifier: Apache-2.0
38 	  v2 ISA for the ARC-HS & ARC-EM cores
66 	  If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision
67 	  floating-point extension
73 	  If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision
74 	  floating-point and double assist instructions
135 	  - LPcc instruction
136 	  - LP_COUNT core reg
137 	  - LP_START, LP_END aux regs
144 	  Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1.
153 	  Interrupts available will be 0 to NUM_IRQS-1.
174 	  to use second register bank - otherwise all interrupts will use
186 	  with highest priority, status32 and pc will be saved in aux regs,
239 	  - The ARC stack checking, or
240 	  - the MPU-based stack guard
245 	  prioritized over the MPU-based stack guard.
262 	  RGF_NUM_BANKS the parameter is disabled by-default because banks syncronization
286 	bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
289 	  Depending on the configuration, CPU can contain accumulator reg-pair
386 	bool "Make early stage SoC-specific initialization"
388 	  Call SoC per-core setup code on early stage initialization