Lines Matching +full:120 +full:- +full:pin

2 # SPDX-License-Identifier: Apache-2.0
7 	bool "Support for external, SPI-connected RAM"
59 	bool "ESP-PSRAM16 or APS1604"
63 	bool "ESP-PSRAM32 or IS25WP032"
67 	bool "ESP-PSRAM64, LY68L6400 or APS6408"
103 	bool "120MHz clock speed"
110 	default 120 if SPIRAM_SPEED_120M
135 	bool "Move Read-Only Data in Flash to PSRAM"
149 	  Enable MSPI Error-Correcting Code function when accessing SPIRAM.
150 	  If enabled, 1/16 of the SPI RAM total size will be reserved for error-correcting code.
154 menu "PSRAM clock and cs IO for ESP32-DOWD"
172 endmenu # PSRAM clock and cs IO for ESP32-DOWD
174 menu "PSRAM clock and cs IO for ESP32-D2WD"
181 …User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
189 …User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
192 endmenu # PSRAM clock and cs IO for ESP32-D2WD
194 menu "PSRAM clock and cs IO for ESP32-PICO"
203 	  For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
205 	  https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
207 endmenu # PSRAM clock and cs IO for ESP32-PICO
210 	bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
217 …When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
218 	  ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
219 	  mode, so a WP pin setting is necessary.
221 	  If this config item is set to N (default), the correct WP pin will be automatically used for any
223 	  to Y and specify the GPIO number connected to the WP pin.
225 …When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP p…
229 	int "Custom SPI PSRAM WP(SD3) Pin"
234 	  The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
237 	  value to the GPIO number of the SPIRAM WP pin.