Lines Matching refs:dmic
37 int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *spec_config);
115 static void dai_dmic_update_bits(const struct dai_intel_dmic *dmic, in dai_dmic_update_bits() argument
118 uint32_t dest = dmic->reg_base + reg; in dai_dmic_update_bits()
123 static inline void dai_dmic_write(const struct dai_intel_dmic *dmic, in dai_dmic_write() argument
126 sys_write32(val, dmic->reg_base + reg); in dai_dmic_write()
129 static inline uint32_t dai_dmic_read(const struct dai_intel_dmic *dmic, in dai_dmic_read() argument
132 return sys_read32(dmic->reg_base + reg); in dai_dmic_read()
136 static inline void dai_dmic_claim_ownership(const struct dai_intel_dmic *dmic) in dai_dmic_claim_ownership() argument
139 sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | in dai_dmic_claim_ownership()
140 FIELD_PREP(DMICLCTL_OSEL, 0x3), dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_claim_ownership()
143 static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic) in dai_dmic_release_ownership() argument
146 sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & in dai_dmic_release_ownership()
147 ~DMICLCTL_OSEL, dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_release_ownership()
152 static inline void dai_dmic_claim_ownership(const struct dai_intel_dmic *dmic) {} in dai_dmic_claim_ownership() argument
153 static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic) {} in dai_dmic_release_ownership() argument
157 static inline uint32_t dai_dmic_base(const struct dai_intel_dmic *dmic) in dai_dmic_base() argument
160 return dmic->hdamldmic_base; in dai_dmic_base()
162 return dmic->shim_base; in dai_dmic_base()
167 static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_intel_dmic *dmic) in dai_dmic_set_sync_period() argument
170 uint32_t base = dai_dmic_base(dmic); in dai_dmic_set_sync_period()
193 static inline void dai_dmic_clear_sync_period(const struct dai_intel_dmic *dmic) in dai_dmic_clear_sync_period() argument
195 uint32_t base = dai_dmic_base(dmic); in dai_dmic_clear_sync_period()
204 static inline void dai_dmic_sync_prepare(const struct dai_intel_dmic *dmic) in dai_dmic_sync_prepare() argument
206 uint32_t base = dai_dmic_base(dmic); in dai_dmic_sync_prepare()
213 static void dmic_sync_trigger(const struct dai_intel_dmic *dmic) in dmic_sync_trigger() argument
215 uint32_t base = dai_dmic_base(dmic); in dmic_sync_trigger()
231 static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_intel_dmic *dmic) {} in dai_dmic_set_sync_period() argument
232 static inline void dai_dmic_clear_sync_period(const struct dai_intel_dmic *dmic) {} in dai_dmic_clear_sync_period() argument
233 static inline void dai_dmic_sync_prepare(const struct dai_intel_dmic *dmic) {} in dai_dmic_sync_prepare() argument
234 static void dmic_sync_trigger(const struct dai_intel_dmic *dmic) {} in dmic_sync_trigger() argument
238 static void dai_dmic_start_fifo_packers(struct dai_intel_dmic *dmic, int fifo_index) in dai_dmic_start_fifo_packers() argument
242 dai_dmic_update_bits(dmic, fifo_index * PDM_CHANNEL_REGS_SIZE + OUTCONTROL, in dai_dmic_start_fifo_packers()
247 static void dai_dmic_stop_fifo_packers(struct dai_intel_dmic *dmic, in dai_dmic_stop_fifo_packers() argument
251 dai_dmic_update_bits(dmic, fifo_index * PDM_CHANNEL_REGS_SIZE + OUTCONTROL, in dai_dmic_stop_fifo_packers()
261 struct dai_intel_dmic *dmic = ((struct device *)data)->data; in dai_dmic_irq_handler() local
266 val0 = dai_dmic_read(dmic, OUTSTAT); in dai_dmic_irq_handler()
267 val1 = dai_dmic_read(dmic, OUTSTAT + PDM_CHANNEL_REGS_SIZE); in dai_dmic_irq_handler()
272 dai_dmic_write(dmic, OUTSTAT, val0); in dai_dmic_irq_handler()
273 dai_dmic_stop_fifo_packers(dmic, 0); in dai_dmic_irq_handler()
278 dai_dmic_write(dmic, OUTSTAT + PDM_CHANNEL_REGS_SIZE, val1); in dai_dmic_irq_handler()
279 dai_dmic_stop_fifo_packers(dmic, 1); in dai_dmic_irq_handler()
283 static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic) in dai_dmic_dis_clk_gating() argument
287 sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD), in dai_dmic_dis_clk_gating()
288 dmic->vshim_base + DMICLVSCTL_OFFSET); in dai_dmic_dis_clk_gating()
290 sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | DMICLCTL_DCGD), in dai_dmic_dis_clk_gating()
291 dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_dis_clk_gating()
295 static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic) in dai_dmic_en_clk_gating() argument
299 sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD), in dai_dmic_en_clk_gating()
300 dmic->vshim_base + DMICLVSCTL_OFFSET); in dai_dmic_en_clk_gating()
302 sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMICLCTL_DCGD), in dai_dmic_en_clk_gating()
303 dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_en_clk_gating()
308 static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmic, in dai_dmic_program_channel_map() argument
314 uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index; in dai_dmic_program_channel_map()
318 ARG_UNUSED(dmic); in dai_dmic_program_channel_map()
324 static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic) in dai_dmic_en_power() argument
326 uint32_t base = dai_dmic_base(dmic); in dai_dmic_en_power()
338 static inline void dai_dmic_dis_power(const struct dai_intel_dmic *dmic) in dai_dmic_dis_power() argument
340 uint32_t base = dai_dmic_base(dmic); in dai_dmic_dis_power()
346 static int dai_dmic_probe(struct dai_intel_dmic *dmic) in dai_dmic_probe() argument
351 dmic->state = DAI_STATE_NOT_READY; in dai_dmic_probe()
354 dai_dmic_en_power(dmic); in dai_dmic_probe()
357 dai_dmic_dis_clk_gating(dmic); in dai_dmic_probe()
360 dai_dmic_set_sync_period(CONFIG_DAI_DMIC_PLATFORM_SYNC_PERIOD, dmic); in dai_dmic_probe()
363 dai_dmic_claim_ownership(dmic); in dai_dmic_probe()
365 irq_enable(dmic->irq); in dai_dmic_probe()
370 static int dai_dmic_remove(struct dai_intel_dmic *dmic) in dai_dmic_remove() argument
377 irq_disable(dmic->irq); in dai_dmic_remove()
390 dai_dmic_en_clk_gating(dmic); in dai_dmic_remove()
391 dai_dmic_dis_power(dmic); in dai_dmic_remove()
394 dai_dmic_clear_sync_period(dmic); in dai_dmic_remove()
397 dai_dmic_release_ownership(dmic); in dai_dmic_remove()
466 static void dai_dmic_gain_ramp(struct dai_intel_dmic *dmic) in dai_dmic_gain_ramp() argument
487 if (dmic->gain == DMIC_HW_FIR_GAIN_MAX << 11) in dai_dmic_gain_ramp()
490 key = k_spin_lock(&dmic->lock); in dai_dmic_gain_ramp()
495 dmic->startcount++; in dai_dmic_gain_ramp()
496 dmic->gain = q_multsr_sat_32x32(dmic->gain, dmic->gain_coef, Q_SHIFT_GAIN_X_GAIN_COEF); in dai_dmic_gain_ramp()
501 gval = dmic->gain >> 11; in dai_dmic_gain_ramp()
509 dmic->gain = DMIC_HW_FIR_GAIN_MAX << 11; in dai_dmic_gain_ramp()
514 if (!dmic->enable[i]) in dai_dmic_gain_ramp()
517 if (dmic->startcount == DMIC_UNMUTE_CIC) in dai_dmic_gain_ramp()
518 dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, in dai_dmic_gain_ramp()
521 if (dmic->startcount == DMIC_UNMUTE_FIR) { in dai_dmic_gain_ramp()
522 dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE * in dai_dmic_gain_ramp()
523 dmic->dai_config_params.dai_index + FIR_CONTROL, in dai_dmic_gain_ramp()
529 dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE * in dai_dmic_gain_ramp()
530 dmic->dai_config_params.dai_index + OUT_GAIN_LEFT, val); in dai_dmic_gain_ramp()
531 dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE * in dai_dmic_gain_ramp()
532 dmic->dai_config_params.dai_index + OUT_GAIN_RIGHT, val); in dai_dmic_gain_ramp()
534 dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE * in dai_dmic_gain_ramp()
535 dmic->dai_config_params.dai_index + OUT_GAIN_LEFT, in dai_dmic_gain_ramp()
536 dmic->gain_left); in dai_dmic_gain_ramp()
537 dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE * in dai_dmic_gain_ramp()
538 dmic->dai_config_params.dai_index + OUT_GAIN_RIGHT, in dai_dmic_gain_ramp()
539 dmic->gain_right); in dai_dmic_gain_ramp()
543 k_spin_unlock(&dmic->lock, key); in dai_dmic_gain_ramp()
546 static void dai_dmic_start(struct dai_intel_dmic *dmic) in dai_dmic_start() argument
555 key = k_spin_lock(&dmic->lock); in dai_dmic_start()
559 dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, CIC_CONTROL_SOFT_RESET, 0); in dai_dmic_start()
562 dmic->startcount = 0; in dai_dmic_start()
565 dmic->gain_coef = db2lin_fixed(LOGRAMP_CONST_TERM / dmic->unmute_time_ms); in dai_dmic_start()
568 dmic->gain = Q_SHIFT_LEFT(db2lin_fixed(LOGRAMP_START_DB), 20, 30); in dai_dmic_start()
570 dai_dmic_sync_prepare(dmic); in dai_dmic_start()
572 dai_dmic_start_fifo_packers(dmic, dmic->dai_config_params.dai_index); in dai_dmic_start()
575 mic_a = dmic->enable[i] & 1; in dai_dmic_start()
576 mic_b = (dmic->enable[i] & 2) >> 1; in dai_dmic_start()
577 start_fir = dmic->enable[i] > 0; in dai_dmic_start()
585 dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, in dai_dmic_start()
590 dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL, in dai_dmic_start()
596 dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, in dai_dmic_start()
599 dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL, in dai_dmic_start()
603 dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, in dai_dmic_start()
606 dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL, in dai_dmic_start()
611 dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE * in dai_dmic_start()
612 dmic->dai_config_params.dai_index + FIR_CONTROL, in dai_dmic_start()
622 dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, in dai_dmic_start()
626 dai_dmic_read(dmic, dmic_base[i] + CIC_CONTROL)); in dai_dmic_start()
631 dai_dmic_global.active_fifos_mask |= BIT(dmic->dai_config_params.dai_index); in dai_dmic_start()
632 dai_dmic_global.pause_mask &= ~BIT(dmic->dai_config_params.dai_index); in dai_dmic_start()
634 dmic->state = DAI_STATE_RUNNING; in dai_dmic_start()
635 k_spin_unlock(&dmic->lock, key); in dai_dmic_start()
637 dmic_sync_trigger(dmic); in dai_dmic_start()
643 static void dai_dmic_stop(struct dai_intel_dmic *dmic, bool stop_is_pause) in dai_dmic_stop() argument
649 key = k_spin_lock(&dmic->lock); in dai_dmic_stop()
651 dai_dmic_stop_fifo_packers(dmic, dmic->dai_config_params.dai_index); in dai_dmic_stop()
661 dai_dmic_global.active_fifos_mask &= ~BIT(dmic->dai_config_params.dai_index); in dai_dmic_stop()
663 dai_dmic_global.pause_mask |= BIT(dmic->dai_config_params.dai_index); in dai_dmic_stop()
665 dai_dmic_global.pause_mask &= ~BIT(dmic->dai_config_params.dai_index); in dai_dmic_stop()
670 dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, in dai_dmic_stop()
676 dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE * in dai_dmic_stop()
677 dmic->dai_config_params.dai_index + FIR_CONTROL, in dai_dmic_stop()
682 k_spin_unlock(&dmic->lock, key); in dai_dmic_stop()
689 const struct dai_intel_dmic *dmic = (const struct dai_intel_dmic *)dev->data; in dai_dmic_get_properties() local
692 prop->fifo_address = dmic->fifo.offset; in dai_dmic_get_properties()
693 prop->fifo_depth = dmic->fifo.depth; in dai_dmic_get_properties()
694 prop->dma_hs_id = dmic->fifo.handshake; in dai_dmic_get_properties()
703 struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data; in dai_dmic_trigger() local
714 if (dmic->state == DAI_STATE_PAUSED || in dai_dmic_trigger()
715 dmic->state == DAI_STATE_PRE_RUNNING) { in dai_dmic_trigger()
716 dai_dmic_start(dmic); in dai_dmic_trigger()
717 dmic->state = DAI_STATE_RUNNING; in dai_dmic_trigger()
720 dmic->state); in dai_dmic_trigger()
724 dai_dmic_stop(dmic, false); in dai_dmic_trigger()
725 dmic->state = DAI_STATE_PRE_RUNNING; in dai_dmic_trigger()
728 dai_dmic_stop(dmic, true); in dai_dmic_trigger()
729 dmic->state = DAI_STATE_PAUSED; in dai_dmic_trigger()
732 dai_dmic_gain_ramp(dmic); in dai_dmic_trigger()
743 struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data; in dai_dmic_get_config() local
753 *cfg = dmic->dai_config_params; in dai_dmic_get_config()
762 struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data; in dai_dmic_set_config() local
764 int di = dmic->dai_config_params.dai_index; in dai_dmic_set_config()
779 dai_dmic_program_channel_map(dmic, cfg, di); in dai_dmic_set_config()
781 key = k_spin_lock(&dmic->lock); in dai_dmic_set_config()
787 ret = dai_dmic_set_config_nhlt(dmic, bespoke_cfg); in dai_dmic_set_config()
790 dmic->unmute_time_ms = dmic_get_unmute_ramp_from_samplerate(dmic->dai_config_params.rate); in dai_dmic_set_config()
800 dmic->state = DAI_STATE_PRE_RUNNING; in dai_dmic_set_config()
803 k_spin_unlock(&dmic->lock, key); in dai_dmic_set_config()
809 struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data; in dai_dmic_probe_wrapper() local
813 key = k_spin_lock(&dmic->lock); in dai_dmic_probe_wrapper()
815 if (dmic->sref == 0) { in dai_dmic_probe_wrapper()
816 ret = dai_dmic_probe(dmic); in dai_dmic_probe_wrapper()
820 dmic->sref++; in dai_dmic_probe_wrapper()
823 k_spin_unlock(&dmic->lock, key); in dai_dmic_probe_wrapper()
830 struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data; in dai_dmic_remove_wrapper() local
834 key = k_spin_lock(&dmic->lock); in dai_dmic_remove_wrapper()
836 if (--dmic->sref == 0) { in dai_dmic_remove_wrapper()
837 ret = dai_dmic_remove(dmic); in dai_dmic_remove_wrapper()
840 k_spin_unlock(&dmic->lock, key); in dai_dmic_remove_wrapper()