82 	unsigned long status = csr_read(mstatus);  in nds_cctl_range_operations()
111 	unsigned long status = csr_read(mstatus);  in nds_l1i_cache_all()
113 	if (csr_read(NDS_MMSC_CFG) & MMSC_CFG_VCCTL_2) {  in nds_l1i_cache_all()
124 		sets = 0x40 << (csr_read(NDS_MICM_CFG) & MICM_CFG_ISET);  in nds_l1i_cache_all()
125 		ways = ((csr_read(NDS_MICM_CFG) >> MICM_CFG_IWAY_SHIFT) & BIT_MASK(3)) + 1;  in nds_l1i_cache_all()
139 	unsigned long status = csr_read(mstatus);  in nds_l1d_cache_all()
141 	if (csr_read(NDS_MMSC_CFG) & MMSC_CFG_VCCTL_2) {  in nds_l1d_cache_all()
216 		if (csr_read(NDS_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {  in cache_data_enable()
218 			while (!(csr_read(NDS_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)) {  in cache_data_enable()
230 	unsigned long status = csr_read(mstatus);  in cache_data_disable()
236 	if (csr_read(NDS_MMSC_CFG) & MMSC_CFG_VCCTL_2) {  in cache_data_disable()
255 		if (csr_read(NDS_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA) {  in cache_data_disable()
258 			while (csr_read(NDS_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA) {  in cache_data_disable()
330 			if (csr_read(NDS_MMSC_CFG) & MMSC_CFG_RVARCH) {  in cache_instr_invd_all()
331 				if (csr_read(NDS_MRVARCH_CFG) & MRVARCH_CFG_SMEPMP) {  in cache_instr_invd_all()
336 			if ((csr_read(NDS_MMSC_CFG) & MMSC_CFG_MSC_EXT) &&  in cache_instr_invd_all()
337 				(csr_read(NDS_MMSC_CFG2) & MMSC_CFG2_RVARCH)) {  in cache_instr_invd_all()
338 				if (csr_read(NDS_MRVARCH_CFG) & MRVARCH_CFG_SMEPMP) {  in cache_instr_invd_all()
489 		line_size = (csr_read(NDS_MICM_CFG) >> MICM_CFG_ISZ_SHIFT) & BIT_MASK(3);  in andes_cache_init()
514 		line_size = (csr_read(NDS_MDCM_CFG) >> MDCM_CFG_DSZ_SHIFT) & BIT_MASK(3);  in andes_cache_init()
537 	if (!(csr_read(NDS_MMSC_CFG) & MMSC_CFG_CCTLCSR)) {  in andes_cache_init()
541 	if (csr_read(NDS_MMSC_CFG) & MMSC_CFG_VCCTL_2) {  in andes_cache_init()