102 	int tt;  member
105 	{ .tt = 0x02, .desc = "illegal_instruction", },
106 	{ .tt = 0x07, .desc = "mem_address_not_aligned", },
107 	{ .tt = 0x2B, .desc = "data_store_error", },
108 	{ .tt = 0x29, .desc = "data_access_error", },
109 	{ .tt = 0x09, .desc = "data_access_exception", },
110 	{ .tt = 0x21, .desc = "instruction_access_error", },
111 	{ .tt = 0x01, .desc = "instruction_access_exception", },
112 	{ .tt = 0x04, .desc = "fp_disabled", },
113 	{ .tt = 0x08, .desc = "fp_exception", },
114 	{ .tt = 0x2A, .desc = "division_by_zero", },
115 	{ .tt = 0x03, .desc = "privileged_instruction", },
116 	{ .tt = 0x20, .desc = "r_register_access_error", },
117 	{ .tt = 0x0B, .desc = "watchpoint_detected", },
118 	{ .tt = 0x2C, .desc = "data_access_MMU_miss", },
119 	{ .tt = 0x3C, .desc = "instruction_access_MMU_miss", },
120 	{ .tt = 0x05, .desc = "window_overflow", },
121 	{ .tt = 0x06, .desc = "window_underflow", },
122 	{ .tt = 0x0A, .desc = "tag_overflow", },
127 	const int tt = (esf->tbr & TBR_TT) >> TBR_TT_BIT;  in print_trap_type()  local
130 	if (tt & 0x80) {  in print_trap_type()
132 	} else if (tt >= 0x11 && tt <= 0x1F) {  in print_trap_type()
136 			if (TTDESC[i].tt == tt) {  in print_trap_type()
142 	LOG_ERR("tt = 0x%02X, %s", tt, desc);  in print_trap_type()