48 	struct pcie_ecam_data *data = dev->data;  in pcie_ecam_init()  local
89 			data->regions[PCIE_REGION_IO].bus_start = cfg->ranges[i].pcie_bus_addr;  in pcie_ecam_init()
90 			data->regions[PCIE_REGION_IO].phys_start = cfg->ranges[i].host_map_addr;  in pcie_ecam_init()
91 			data->regions[PCIE_REGION_IO].size = cfg->ranges[i].map_length;  in pcie_ecam_init()
93 			if (data->regions[PCIE_REGION_IO].bus_start < 0x1000) {  in pcie_ecam_init()
94 				data->regions[PCIE_REGION_IO].allocation_offset = 0x1000;  in pcie_ecam_init()
98 			data->regions[PCIE_REGION_MEM].bus_start = cfg->ranges[i].pcie_bus_addr;  in pcie_ecam_init()
99 			data->regions[PCIE_REGION_MEM].phys_start = cfg->ranges[i].host_map_addr;  in pcie_ecam_init()
100 			data->regions[PCIE_REGION_MEM].size = cfg->ranges[i].map_length;  in pcie_ecam_init()
102 			if (data->regions[PCIE_REGION_MEM].bus_start < 0x1000) {  in pcie_ecam_init()
103 				data->regions[PCIE_REGION_MEM].allocation_offset = 0x1000;  in pcie_ecam_init()
107 			data->regions[PCIE_REGION_MEM64].bus_start = cfg->ranges[i].pcie_bus_addr;  in pcie_ecam_init()
108 			data->regions[PCIE_REGION_MEM64].phys_start = cfg->ranges[i].host_map_addr;  in pcie_ecam_init()
109 			data->regions[PCIE_REGION_MEM64].size = cfg->ranges[i].map_length;  in pcie_ecam_init()
111 			if (data->regions[PCIE_REGION_MEM64].bus_start < 0x1000) {  in pcie_ecam_init()
112 				data->regions[PCIE_REGION_MEM64].allocation_offset = 0x1000;  in pcie_ecam_init()
118 	if (!data->regions[PCIE_REGION_IO].size &&  in pcie_ecam_init()
119 	    !data->regions[PCIE_REGION_MEM].size &&  in pcie_ecam_init()
120 	    !data->regions[PCIE_REGION_MEM64].size) {  in pcie_ecam_init()
126 	data->cfg_phys_addr = cfg->cfg_addr;  in pcie_ecam_init()
127 	data->cfg_size = cfg->cfg_size;  in pcie_ecam_init()
129 	if (data->regions[PCIE_REGION_IO].size) {  in pcie_ecam_init()
131 			data->regions[PCIE_REGION_IO].bus_start,  in pcie_ecam_init()
132 			(data->regions[PCIE_REGION_IO].bus_start +  in pcie_ecam_init()
133 			 data->regions[PCIE_REGION_IO].size - 1),  in pcie_ecam_init()
134 			data->regions[PCIE_REGION_IO].size);  in pcie_ecam_init()
136 			data->regions[PCIE_REGION_IO].phys_start,  in pcie_ecam_init()
137 			(data->regions[PCIE_REGION_IO].phys_start +  in pcie_ecam_init()
138 			 data->regions[PCIE_REGION_IO].size - 1),  in pcie_ecam_init()
139 			data->regions[PCIE_REGION_IO].size);  in pcie_ecam_init()
141 	if (data->regions[PCIE_REGION_MEM].size) {  in pcie_ecam_init()
143 			data->regions[PCIE_REGION_MEM].bus_start,  in pcie_ecam_init()
144 			(data->regions[PCIE_REGION_MEM].bus_start +  in pcie_ecam_init()
145 			 data->regions[PCIE_REGION_MEM].size - 1),  in pcie_ecam_init()
146 			data->regions[PCIE_REGION_MEM].size);  in pcie_ecam_init()
148 			data->regions[PCIE_REGION_MEM].phys_start,  in pcie_ecam_init()
149 			(data->regions[PCIE_REGION_MEM].phys_start +  in pcie_ecam_init()
150 			 data->regions[PCIE_REGION_MEM].size - 1),  in pcie_ecam_init()
151 			data->regions[PCIE_REGION_MEM].size);  in pcie_ecam_init()
153 	if (data->regions[PCIE_REGION_MEM64].size) {  in pcie_ecam_init()
155 			data->regions[PCIE_REGION_MEM64].bus_start,  in pcie_ecam_init()
156 			(data->regions[PCIE_REGION_MEM64].bus_start +  in pcie_ecam_init()
157 			 data->regions[PCIE_REGION_MEM64].size - 1),  in pcie_ecam_init()
158 			data->regions[PCIE_REGION_MEM64].size);  in pcie_ecam_init()
160 			data->regions[PCIE_REGION_MEM64].phys_start,  in pcie_ecam_init()
161 			(data->regions[PCIE_REGION_MEM64].phys_start +  in pcie_ecam_init()
162 			 data->regions[PCIE_REGION_MEM64].size - 1),  in pcie_ecam_init()
163 			data->regions[PCIE_REGION_MEM64].size);  in pcie_ecam_init()
167 	device_map(&data->cfg_addr, data->cfg_phys_addr, data->cfg_size, K_MEM_CACHE_NONE);  in pcie_ecam_init()
170 		data->cfg_phys_addr, (data->cfg_phys_addr + data->cfg_size - 1), data->cfg_size);  in pcie_ecam_init()
172 		data->cfg_addr, (data->cfg_addr + data->cfg_size - 1), data->cfg_size);  in pcie_ecam_init()
181 	struct pcie_ecam_data *data = dev->data;  in pcie_ecam_ctrl_conf_read()  local
183 	return pcie_generic_ctrl_conf_read(data->cfg_addr, bdf, reg);  in pcie_ecam_ctrl_conf_read()
189 	struct pcie_ecam_data *data = dev->data;  in pcie_ecam_ctrl_conf_write()  local
191 	pcie_generic_ctrl_conf_write(data->cfg_addr, bdf, reg, reg_data);  in pcie_ecam_ctrl_conf_write()
194 static bool pcie_ecam_region_allocate_type(struct pcie_ecam_data *data, pcie_bdf_t bdf,  in pcie_ecam_region_allocate_type()  argument
200 	addr = (((data->regions[type].bus_start + data->regions[type].allocation_offset) - 1) |  in pcie_ecam_region_allocate_type()
203 	if (addr - data->regions[type].bus_start + bar_size > data->regions[type].size) {  in pcie_ecam_region_allocate_type()
208 	data->regions[type].allocation_offset = addr - data->regions[type].bus_start + bar_size;  in pcie_ecam_region_allocate_type()
217 	struct pcie_ecam_data *data = dev->data;  in pcie_ecam_region_allocate()  local
220 	if (mem && !data->regions[PCIE_REGION_MEM64].size &&  in pcie_ecam_region_allocate()
221 	    !data->regions[PCIE_REGION_MEM].size) {  in pcie_ecam_region_allocate()
226 	if (!mem && !data->regions[PCIE_REGION_IO].size) {  in pcie_ecam_region_allocate()
237 	if (mem && ((mem64 && data->regions[PCIE_REGION_MEM64].size) ||  in pcie_ecam_region_allocate()
238 		    (data->regions[PCIE_REGION_MEM64].size &&  in pcie_ecam_region_allocate()
239 		     !data->regions[PCIE_REGION_MEM].size))) {  in pcie_ecam_region_allocate()
247 	return pcie_ecam_region_allocate_type(data, bdf, bar_size, bar_bus_addr, type);  in pcie_ecam_region_allocate()
254 	struct pcie_ecam_data *data = (struct pcie_ecam_data *)dev->data;  in pcie_ecam_region_get_allocate_base()  local
257 	if (mem && !data->regions[PCIE_REGION_MEM64].size &&  in pcie_ecam_region_get_allocate_base()
258 	    !data->regions[PCIE_REGION_MEM].size) {  in pcie_ecam_region_get_allocate_base()
263 	if (!mem && !data->regions[PCIE_REGION_IO].size) {  in pcie_ecam_region_get_allocate_base()
274 	if (mem && ((mem64 && data->regions[PCIE_REGION_MEM64].size) ||  in pcie_ecam_region_get_allocate_base()
275 		    (data->regions[PCIE_REGION_MEM64].size &&  in pcie_ecam_region_get_allocate_base()
276 		     !data->regions[PCIE_REGION_MEM].size))) {  in pcie_ecam_region_get_allocate_base()
284 	*bar_base_addr = (((data->regions[type].bus_start +  in pcie_ecam_region_get_allocate_base()
285 			    data->regions[type].allocation_offset) - 1) | ((align) - 1)) + 1;  in pcie_ecam_region_get_allocate_base()
294 	struct pcie_ecam_data *data = dev->data;  in pcie_ecam_region_translate()  local
302 	if (mem && ((mem64 && data->regions[PCIE_REGION_MEM64].size) ||  in pcie_ecam_region_translate()
303 		    (data->regions[PCIE_REGION_MEM64].size &&  in pcie_ecam_region_translate()
304 		     !data->regions[PCIE_REGION_MEM].size))) {  in pcie_ecam_region_translate()
312 	*bar_addr = data->regions[type].phys_start + (bar_bus_addr - data->regions[type].bus_start);  in pcie_ecam_region_translate()