Lines Matching +full:0 +full:x40
21 #size-cells = <0>;
22 cpu0: cpu@0 {
23 reg = <0>;
29 #address-cells = <0>;
42 ram_ilm: memory@0 {
52 reg = <0xe6000000 0x10000>;
53 interrupts = <7 0>;
59 reg = <0x80140100 0x40>;
72 reg = <0x80140180 0x40>;
83 reg = <0x80140300 0x08>;
93 reg = <0x80140308 0x08>;
103 reg = <0x80140310 0x08>;
113 reg = <0x80140318 0x08>;
123 reg = <0x80140320 0x08>;
129 compatible = "sifive,plic-1.0.0";
130 #address-cells = <0>;
135 reg = <0xe4000000 0x00210000>;
142 reg = <0x80140080 0x40>;
150 reg = <0x801400C0 0x40>;
158 reg = <0x80140800 0x800>;
166 reg = <0x80101800 0x20>;
172 reg = <0x80140400 0x80>;
180 reg = <0x81FFFFC0 0x40>;
182 cs0-pin = "0";
183 cs1-pin = "0";
184 cs2-pin = "0";
186 #size-cells = <0>;
192 reg = <0x80140040 0x40>;
194 cs0-pin = "0";
195 cs1-pin = "0";
196 cs2-pin = "0";
198 #size-cells = <0>;
204 reg = <0x80140280 0x40>;
206 #size-cells = <0>;
213 reg = <0xea 0x18>;
220 reg = <0x80140330 0x28
221 0x80140306 0x28
222 0x0000000e 0x0C>;