Lines Matching +full:0 +full:x40
22 #size-cells = <0>;
23 cpu@0 {
27 reg = <0>;
40 reg = <0x20000000 0x30000>;
45 reg = <0x09000000 0x20000>;
62 reg = <0x4002b000 0x200>;
68 reg = <0x41027000 0x200>;
74 #address-cells = <0>;
77 reg = <0xe0041000 0x88>;
82 #address-cells = <0>;
85 reg = <0x4101f000 0x88>;
90 reg = <0x4004f000 0x200>;
91 clocks = <&pcc0 0x13c>;
96 ranges = <0x0 0x4004f000 0x200>;
98 intmux0_ch0: interrupt-controller@0 {
100 #address-cells = <0>;
104 reg = <0x0 0x40>;
110 #address-cells = <0>;
114 reg = <0x40 0x40>;
120 #address-cells = <0>;
124 reg = <0x80 0x40>;
130 #address-cells = <0>;
134 reg = <0xc0 0x40>;
140 #address-cells = <0>;
144 reg = <0x100 0x40>;
150 #address-cells = <0>;
154 reg = <0x140 0x40>;
160 #address-cells = <0>;
164 reg = <0x180 0x40>;
170 #address-cells = <0>;
174 reg = <0x1c0 0x40>;
181 reg = <0x41022000 0x20>;
182 clocks = <&pcc1 0x88>;
187 ranges = <0x0 0x41022000 0x200>;
189 intmux1_ch0: interrupt-controller@0 {
191 #address-cells = <0>;
195 reg = <0x0 0x40>;
201 #address-cells = <0>;
205 reg = <0x40 0x40>;
211 #address-cells = <0>;
215 reg = <0x80 0x40>;
221 #address-cells = <0>;
225 reg = <0xc0 0x40>;
231 #address-cells = <0>;
235 reg = <0x100 0x40>;
241 #address-cells = <0>;
245 reg = <0x140 0x40>;
251 #address-cells = <0>;
255 reg = <0x180 0x40>;
261 #address-cells = <0>;
265 reg = <0x1c0 0x40>;
272 reg = <0x40032000 0x10>;
277 reg = <0x40033000 0x10>;
282 reg = <0x4102b000 0x10>;
287 reg = <0x40046000 0xd0>;
288 clocks = <&pcc0 0x118>;
293 reg = <0x40047000 0xd0>;
294 clocks = <&pcc0 0x11c>;
299 reg = <0x40048000 0xd0>;
300 clocks = <&pcc0 0x120>;
305 reg = <0x40049000 0xd0>;
306 clocks = <&pcc0 0x124>;
311 reg = <0x41037000 0xd0>;
312 clocks = <&pcc1 0xdc>;
317 reg = <0x48020000 0x14>;
325 reg = <0x48020040 0x14>;
333 reg = <0x48020080 0x14>;
341 reg = <0x480200c0 0x14>;
349 reg = <0x4100f000 0x14>;
352 clocks = <&pcc1 0x3c>;
358 reg = <0x40042000 0x2c>;
359 clocks = <&pcc0 0x108>;
365 reg = <0x40043000 0x2c>;
366 clocks = <&pcc0 0x10c>;
372 reg = <0x40044000 0x2c>;
373 clocks = <&pcc0 0x110>;
379 reg = <0x41036000 0x2c>;
380 clocks = <&pcc0 0xd8>;
386 reg = <0x4003a000 0x170>;
387 clocks = <&pcc0 0xe8>;
390 #size-cells = <0>;
396 reg = <0x4003b000 0x170>;
397 clocks = <&pcc0 0xec>;
400 #size-cells = <0>;
406 reg = <0x4003c000 0x170>;
407 clocks = <&pcc0 0xf0>;
410 #size-cells = <0>;
416 reg = <0x4102e000 0x170>;
417 clocks = <&pcc1 0xb8>;
420 #size-cells = <0>;
426 reg = <0x4003f000 0x78>;
428 clocks = <&pcc0 0xfc>;
430 #size-cells = <0>;
435 reg = <0x40040000 0x78>;
437 clocks = <&pcc0 0x100>;
439 #size-cells = <0>;
444 reg = <0x40041000 0x78>;
446 clocks = <&pcc0 0x104>;
448 #size-cells = <0>;
453 reg = <0x41035000 0x78>;
455 clocks = <&pcc1 0xd4>;
457 #size-cells = <0>;
462 reg = <0x41033000 0x90>;
464 #size-cells = <0>;
469 reg = <0x40035000 0x88>;
470 clocks = <&pcc0 0xd4>;
477 reg = <0x40036000 0x88>;
478 clocks = <&pcc0 0xd8>;
485 reg = <0x40037000 0x88>;
486 clocks = <&pcc0 0xdc>;
493 reg = <0x41029000 0x1000>;
495 interrupts = <13 0>;
500 reg = <0x4102d000 0x88>;
501 clocks = <&pcc1 0xb4>;
508 reg = <0x40023000 0x18>;
513 m4_flash: flash@0 {
515 reg = <0 0x100000>;
522 reg = <0x01000000 0x40000>;