Lines Matching +full:gpio +full:- +full:width

1 description: Xilinx AXI GPIO IP node
3 compatible: "xlnx,xps-gpio-1.00.a"
5 include: [gpio-controller.yaml, base.yaml]
7 bus: xlnx,xps-gpio-1.00.a
10 # https://github.com/Xilinx/device-tree-xlnx
16   xlnx,all-inputs:
21   xlnx,all-outputs:
26   xlnx,dout-default:
29       Default output value. If n-th bit is 1, GPIO-n default value is 1.
31   xlnx,gpio-width:
36   xlnx,tri-default:
39       Default tristate register value. If n-th bit is 1, GPIO-n is an input.
41   xlnx,is-dual:
46   xlnx,all-inputs-2:
51   xlnx,all-outputs-2:
56   xlnx,dout-default-2:
59       Default output value. If n-th bit is 1, GPIO2-n default value is 1.
61   xlnx,gpio2-width:
66   xlnx,tri-default-2:
69       Default tristate register value. If n-th bit is 1, GPIO2-n is an input.
71   "#gpio-cells":
74 gpio-cells:
75   - pin
76   - flags