Lines Matching +full:gpio +full:- +full:controller

1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
5   NXP S32 GPIO controller.
7   The GPIO controller provides the option to route external input pad interrupts
8   to either the SIUL2 EIRQ interrupt controller or, when available on the SoC,
9   the WKPU interrupt controller. By default, GPIO interrupts are routed to the
10   SIUL2 EIRQ interrupt controller.
12   To route external interrupts to the WKPU interrupt controller, the GPIO
14   the following snippet of devicetree source code instructs the GPIO controller
15   to route the interrupt from pin 9 of `gpioa` to the WKPU interrupt controller:
17     #include <zephyr/dt-bindings/gpio/nxp-s32-gpio.h>
23   Explicitly specifying the routing of a GPIO interrupt to a particular
24   interrupt controller allows for the allocation of distinct interrupt
25   priorities according to application-specific requirements. This is owing to
26   the fact that each interrupt controller features its own interrupt vector.
28   the interrupt controller configured with a lower priority compared to the one
29   designated for the data-ready interrupt originating from a sensor. This
34   as the interrupt controller for the corresponding GPIO. It's worth noting that
35   despite being named WKPU, the flag is not meant to configure GPIOs as wake-up
38 compatible: "nxp,s32-gpio"
40 include: [gpio-controller.yaml, base.yaml]
46   reg-names:
51       For GPIO ports that have pins can be used for processing
52       external interrupt signal, this is a list of GPIO pins and
53       respective external interrupt lines (<gpio-pin eirq-line>).
58       NXP WKPU controller associated to this GPIO port.
60   nxp,wkpu-interrupts:
63       Map between WKPU external interrupt sources and pins of this GPIO port,
64       as in a tuple `<gpio-pin wkpu-interrupt-source>`.
66   "#gpio-cells":
69 gpio-cells:
70   - pin
71   - flags