Lines Matching +full:mode +full:- +full:gpios

2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "lattice,ice40-fpga"
8 include: spi-device.yaml
11   load-mode:
18       1 := load the FPGA via bit-banged GPIO
19       Option 0 may be suitable for some high-end microcontrollers.
20       Option 1 is suitable for low-end microcontrollers. This option
21       requires clk-gpios, pico-gpios, gpios-set-reg, and gpios-clear-reg
24       load-mode = <0>;
25   cdone-gpios:
26     type: phandle-array
31       cdone-gpios = <&gpio0 0 0>;
32   creset-gpios:
33     type: phandle-array
38       creset-gpios = <&gpio0 1 GPIO_PUSH_PULL);
39   clk-gpios:
40     type: phandle-array
44       clk-gpios = <&gpio0 5 GPIO_PUSH_PULL>;
45   pico-gpios:
46     type: phandle-array
48       Peripheral-In Controller-Out GPIO input on iCE40.
50       pico-gpios = <&gpio0 7 GPIO_PUSH_PULL>;
51   gpios-set-reg:
56       gpios-set-reg = <0x60004008>;
57   gpios-clear-reg:
62       gpios-clear-reg = <0x6000400c>;
63   mhz-delay-count:
70         for(int i = mhz_delay_count; i > 0; --i);
72         for(int i = mhz_delay_count; i > 0; --i);
75       mhz-delay-count = <0>;
76   creset-delay-us:
81       creset-delay-us = <1>;
82   config-delay-us:
87       config-delay-us = <1200>;
88   leading-clocks:
93       leading-clocks = <8>;
94   trailing-clocks:
99       trailing-clocks = <49>;