Lines Matching +full:3 +full:- +full:cell

2 # SPDX-License-Identifier: Apache-2.0
10     - bit 6-7:   Direction  (see dma.h)
11                  - 0x0: MEMORY to MEMORY
12                  - 0x1: MEMORY to PERIPH
13                  - 0x2: PERIPH to MEMORY
14                  - 0x3: reserved for PERIPH to PERIPH
16     - bit 9:     Peripheral address increase
17                  - 0x0: no address increment between transfers
18                  - 0x1: increment address between transfers
20     - bit 10:    Memory address increase
21                  - 0x0: no address increase between transfers
22                  - 0x1: increase address between transfers
24     - bit 11-12: Peripheral data width
25                  - 0x0: 8 bits
26                  - 0x1: 16 bits
27                  - 0x2: 32 bits
28                  - 0x3: reserved
30     - bit 13-14: Memory data width
31                  - 0x0: 8 bits
32                  - 0x1: 16 bits
33                  - 0x2: 32 bits
34                  - 0x3: reserved
36     - bit 15:    Peripheral Increment Offset Size
37                  - 0x0: offset size is linked to the peripheral bus width
38                  - 0x1: offset size is fixed to 4 (32-bit alignment)
40     - bit 16-17: Priority
41                  - 0x0: low
42                  - 0x1: medium
43                  - 0x2: high
44                  - 0x3: very high
50         pinctrl-0 = <&spi0_default>;
51         pinctrl-names = "default";
52         cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
54         dmas = <&dma0 3 0>, <&dma0 5 GD32_DMA_PRIORITY_HIGH>;
55         dma-names = "rx", "tx";
60   The channel cell assigns channel 3 to receive and channel 5 to transmit.
61   The config cell can take various configs.
65 compatible: "gd,gd32-dma"
67 include: ["gd,gd32-dma-base.yaml"]
70   "#dma-cells":
73 dma-cells:
74   - channel
75   - config