Lines Matching +full:0 +full:x3

13                  - 0x0: MEMORY to MEMORY
14                  - 0x1: MEMORY to PERIPH
15                  - 0x2: PERIPH to MEMORY
16                  - 0x3: reserved for PERIPH to PERIPH
19                  - 0x0: no address increment between transfers
20                  - 0x1: increment address between transfers
23                  - 0x0: no address increase between transfers
24                  - 0x1: increase address between transfers
27                  - 0x0: 8 bits
28                  - 0x1: 16 bits
29                  - 0x2: 32 bits
30                  - 0x3: reserved
33                  - 0x0: 8 bits
34                  - 0x1: 16 bits
35                  - 0x2: 32 bits
36                  - 0x3: reserved
39                  - 0x0: offset size is linked to the peripheral bus width
40                  - 0x1: offset size is fixed to 4 (32-bit alignment)
43                  - 0x0: low
44                  - 0x1: medium
45                  - 0x2: high
46                  - 0x3: very high
49     - bit 0-1:   Depth of DMA's FIFO used by burst-transfer.
50                  - 0x0: 1 word
51                  - 0x1: 2 word
52                  - 0x2: 3 word
53                  - 0x3: 4 word
60         pinctrl-0 = <&spi0_default>;
64         dmas = <&dma1 0 3 0 0>, <&dma1 5 3 GD32_DMA_PRIORITY_HIGH 0>
70   The first cell assigns channel 0 to receive and channel 5 to transmit.