Lines Matching full:pclk
15 pclk:
19 The value to divide the main clock by for PCLK. If the
20 typical main clock was 48MHz and this value is 5, the PCLK
27 Polarity of PCLK. If it is set to zero, PCLK polarity is on
28 the rising edge. If it is set to one, PCLK polarity is on
35 Controls the transition of RGB signals with PCLK active clock
37 following the active edge of PCLK. When set to 1, R[7:2]
38 changes a PCLK clock early and B[7:2] a PCLK clock later,
83 description: Number of PCLK cycles per visible part of horizontal line
89 Number of PCLK cycles before pixels are scanned out for
95 description: Number of total PCLK cycles per horizontal line scan.
100 description: Number of PCLK cycles of HSYNC high state during start of
106 description: Number of PCLK cycles for HSYNC toggle during start of line.