Lines Matching +full:0 +full:x00
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0>;
58 #clock-cells = <0>;
70 reg = <0x00 0x8000000 0x00 0x010000>,
71 <0x00 0x80a0000 0x00 0xf60000>;
75 #size-cells = <0x02>;
76 #address-cells = <0x02>;
80 reg = <0x00 0x8080000 0x00 0x20000>;
87 reg = <0x00 0x9000000 0x00 0x1000>;
89 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL 0>;
94 flash0: flash@0 {
101 reg = <0x0 0x0 0x0 DT_SIZE_M(64) /* 0x4000000 DT_SIZE_M(64) */>;
107 reg = <0x40 0x10000000 0x00 0x10000000>;
108 #size-cells = <0x02>;
109 #address-cells = <0x03>;
110 ranges = <0x1000000 0x00 0x00 0x00 0x3eff0000 0x00 0x10000
111 0x2000000 0x00 0x10000000 0x00 0x10000000 0x00 0x2eff0000
112 0x3000000 0x80 0x00 0x80 0x00 0x80 0x00>;
113 #interrupt-cells = <0x01>;
114 interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
115 interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI
116 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
117 0x00 0x00 0x00 2 &gic 0 0 GIC_SPI
118 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
119 0x00 0x00 0x00 3 &gic 0 0 GIC_SPI
120 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
121 0x00 0x00 0x00 4 &gic 0 0 GIC_SPI
122 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
124 0x800 0x00 0x00 1 &gic 0 0 GIC_SPI
125 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
126 0x800 0x00 0x00 2 &gic 0 0 GIC_SPI
127 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
128 0x800 0x00 0x00 3 &gic 0 0 GIC_SPI
129 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
130 0x800 0x00 0x00 4 &gic 0 0 GIC_SPI
131 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
133 0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI
134 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
135 0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI
136 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
137 0x1000 0x00 0x00 3 &gic 0 0 GIC_SPI
138 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
139 0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI
140 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
142 0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI
143 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
144 0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI
145 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
146 0x1800 0x00 0x00 3 &gic 0 0 GIC_SPI
147 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
148 0x1800 0x00 0x00 4 &gic 0 0 GIC_SPI
149 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
151 bus-range = <0x00 0xff>;