Lines Matching +full:0 +full:x70

14 	reg = <0x00000000 DT_SIZE_K(32)>;
18 	reg = <0x20000000 DT_SIZE_K(32)>;
22 	reg = <0x20200000 DT_SIZE_K(64)>;
34 	interrupts = <70 0>, <71 0>;
38 	interrupts = <73 0>;
42 	interrupts = <30 0>;
46 	interrupts = <31 0>;
69 			reg = <0x42000000 0x4000>;
70 			interrupts = <72 0>;
99 			reg = <0x400a0000 0x4000>;
100 			interrupts = <26 0>;
102 			#size-cells = <0>;
119 			#size-cells = <0>;
120 			reg = <0x401a4000 0x4000>;
121 			interrupts = <28 0>;
122 			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 6>;
130 			#size-cells = <0>;
131 			reg = <0x401a8000 0x4000>;
132 			interrupts = <29 0>;
133 			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 8>;
149 			reg = <0x40194000 0x4000>;
152 			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 0>;
154 			#size-cells = <0>;
159 			reg = <0x40198000 0x4000>;
162 			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 2>;
164 			#size-cells = <0>;
183 			reg = <0x401cc000 0x4000>;
184 			interrupts = <38 0>;
188 				index = <0>;
189 				interrupts = <34 0>;
191 				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
199 				interrupts = <35 0>;
201 				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
209 				interrupts = <36 0>;
211 				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
219 				interrupts = <37 0>;
221 				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
238 			reg = <0x400e4000 0x200>;
271 			#size-cells = <0>;
273 			reg = <0x401e0000 0x4000>;
274 			clocks = <&ccm IMX_CCM_SAI1_CLK 0x7C 18>;
279 		       pll-clocks = <&anatop 0x70 0xC000 0>,
280 				      <&anatop 0x70 0x7F 32>,
281 				      <&anatop 0x70 0x180000 1>,
282 				      <&anatop 0x80 0x3FFFFFFF 77>,
283 				      <&anatop 0x90 0x3FFFFFFF 100>;
288 			 * A pre-div value of 0x1 results in a pre-divider of
291 			pre-div = <0x3>;
292 			podf = <0x0F>;
293 			pinmuxes = <&iomuxcgpr 0x4 0x80000>;
294 			interrupts = <56 0>;
295 			dmas = <&edma0 0 19>, <&edma0 0 20>;
298 			 * cannot be 0
301 			nxp,tx-dma-channel = <0>;
309 			#size-cells = <0>;
311 			reg = <0x401e8000 0x4000>;
312 			clocks = <&ccm IMX_CCM_SAI3_CLK 0x7C 22>;
313 			pre-div = <0>;
315 			pll-clocks = <&anatop 0x70 0xC000 0>,
316 				   <&anatop 0x70 0x7F 32>,
317 				   <&anatop 0x70 0x180000 1>,
318 				   <&anatop 0x80 0x3FFFFFFF 77>,
319 				   <&anatop 0x90 0x3FFFFFFF 100>;
321 			pinmuxes = <&iomuxcgpr 0x4 0x200000>;
322 			interrupts = <58 0>, <59 0>;
323 			dmas = <&edma0 0 83>, <&edma0 0 84>;
325 			nxp,tx-channel = <0>;