Lines Matching +full:0 +full:x40
18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
29 reg = <0x1FFFF000 DT_SIZE_K(16)>;
41 reg = <0x40020000 0x14>;
42 interrupts = <5 0>;
48 flash0: flash@0 {
50 reg = <0 DT_SIZE_K(128)>;
58 reg = <0x40064000 0xd>;
66 #size-cells = <0>;
67 reg = <0x40066000 0x1000>;
68 interrupts = <8 0>;
69 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
77 #size-cells = <0>;
78 reg = <0x40067000 0x1000>;
79 interrupts = <9 0>;
80 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
86 reg = <0x40047000 0x1060>;
93 #clock-cells = <0>;
100 #clock-cells = <0>;
106 reg = <0x4006a000 0xc>;
107 interrupts = <12 0>;
108 clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
115 reg = <0x4003b000 0x70>;
116 interrupts = <15 0>;
123 reg = <0x40049000 0xd0>;
124 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
129 reg = <0x4004a000 0xd0>;
130 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
135 reg = <0x4004b000 0xd0>;
136 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
141 reg = <0x4004c000 0xd0>;
142 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
147 reg = <0x4004d000 0xd0>;
148 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
154 reg = <0x400ff000 0x40>;
164 reg = <0x400ff040 0x40>;
173 reg = <0x400ff080 0x40>;
182 reg = <0x400ff0c0 0x40>;
192 reg = <0x400ff100 0x40>;
200 reg = <0x40072000 0x1000>;