Lines Matching +full:0 +full:x40
21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
32 reg = <0x20000000 DT_SIZE_K(512)>;
38 #clock-cells = <0>;
44 reg = <0x40000200 0x100>;
45 #clock-cells = <0>;
60 reg = <0x40000000 0x20>;
67 reg = <0x4000c000 0x110>;
71 flash0: flash@0 {
73 reg = <0 DT_SIZE_K(1024)>;
81 reg = <0x40070000 0x1000>;
82 interrupts = <36 0>;
91 reg = <0x40071000 0x1000>;
92 interrupts = <37 0>;
101 reg = <0x40072000 0x1000>;
102 interrupts = <48 0>;
111 reg = <0x40073000 0x1000>;
112 interrupts = <49 0>;
121 reg = <0x40074000 0x1000>;
122 interrupts = <74 0>;
131 reg = <0x40075000 0x1000>;
132 interrupts = <75 0>;
141 reg = <0x40076000 0x1000>;
142 interrupts = <102 0>;
151 reg = <0x40077000 0x1000>;
152 interrupts = <103 0>;
161 reg = <0x40078000 0x1000>;
162 interrupts = <99 0>;
171 reg = <0x40079000 0x1000>;
172 interrupts = <100 0>;
181 reg = <0x40000080 0x28
182 0x40000500 0xa0>;
191 reg = <0x40004000 0x40>;
192 clocks = <&pcc NUMAKER_GPA_MODULE 0 0>;
201 reg = <0x40004040 0x40>;
202 clocks = <&pcc NUMAKER_GPB_MODULE 0 0>;
211 reg = <0x40004080 0x40>;
212 clocks = <&pcc NUMAKER_GPC_MODULE 0 0>;
221 reg = <0x400040c0 0x40>;
222 clocks = <&pcc NUMAKER_GPD_MODULE 0 0>;
231 reg = <0x40004100 0x40>;
232 clocks = <&pcc NUMAKER_GPE_MODULE 0 0>;
241 reg = <0x40004140 0x40>;
242 clocks = <&pcc NUMAKER_GPF_MODULE 0 0>;
251 reg = <0x40004180 0x40>;
252 clocks = <&pcc NUMAKER_GPG_MODULE 0 0>;
261 reg = <0x400041c0 0x40>;
262 clocks = <&pcc NUMAKER_GPH_MODULE 0 0>;
271 reg = <0x40004200 0x40>;
272 clocks = <&pcc NUMAKER_GPI_MODULE 0 0>;
281 reg = <0x40004240 0x40>;
282 clocks = <&pcc NUMAKER_GPJ_MODULE 0 0>;
289 reg = <0x40061000 0x6c>;
290 interrupts = <23 0>;
292 clocks = <&pcc NUMAKER_SPI0_MODULE NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC 0>;
294 #size-cells = <0>;
300 reg = <0x40062000 0x6c>;
301 interrupts = <51 0>;
303 clocks = <&pcc NUMAKER_SPI1_MODULE NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC 0>;
305 #size-cells = <0>;
311 reg = <0x40063000 0x6c>;
312 interrupts = <52 0>;
314 clocks = <&pcc NUMAKER_SPI2_MODULE NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC 0>;
316 #size-cells = <0>;
322 reg = <0x40064000 0x6c>;
323 interrupts = <62 0>;
325 clocks = <&pcc NUMAKER_SPI3_MODULE NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC 0>;
327 #size-cells = <0>;
333 reg = <0x40065000 0x6c>;
334 interrupts = <63 0>;
336 clocks = <&pcc NUMAKER_SPI4_MODULE NUMAKER_CLK_CLKSEL4_SPI4SEL_HIRC 0>;
338 #size-cells = <0>;
344 reg = <0x40066000 0x6c>;
345 interrupts = <57 0>;
347 clocks = <&pcc NUMAKER_SPI5_MODULE NUMAKER_CLK_CLKSEL4_SPI5SEL_HIRC 0>;
349 #size-cells = <0>;
355 reg = <0x40067000 0x6c>;
356 interrupts = <70 0>;
358 clocks = <&pcc NUMAKER_SPI6_MODULE NUMAKER_CLK_CLKSEL4_SPI6SEL_HIRC 0>;
360 #size-cells = <0>;
366 reg = <0x40068000 0x6c>;
367 interrupts = <77 0>;
369 clocks = <&pcc NUMAKER_SPI7_MODULE NUMAKER_CLK_CLKSEL4_SPI7SEL_HIRC 0>;
371 #size-cells = <0>;
377 reg = <0x4006b000 0x6c>;
378 interrupts = <108 0>;
380 clocks = <&pcc NUMAKER_SPI8_MODULE NUMAKER_CLK_CLKSEL4_SPI8SEL_HIRC 0>;
382 #size-cells = <0>;
388 reg = <0x4006c000 0x6c>;
389 interrupts = <111 0>;
391 clocks = <&pcc NUMAKER_SPI9_MODULE NUMAKER_CLK_CLKSEL4_SPI9SEL_HIRC 0>;
393 #size-cells = <0>;
399 reg = <0x4006d000 0x6c>;
400 interrupts = <119 0>;
402 clocks = <&pcc NUMAKER_SPI10_MODULE NUMAKER_CLK_CLKSEL4_SPI10SEL_HIRC 0>;
404 #size-cells = <0>;
410 reg = <0x40058000 0x37c>;
411 interrupts = <25 0>, <26 0>, <27 0>;
415 clocks = <&pcc NUMAKER_EPWM0_MODULE NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0 0>;
422 reg = <0x40059000 0x37c>;
423 interrupts = <29 0>, <30 0>, <31 0>;
427 clocks = <&pcc NUMAKER_EPWM1_MODULE NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1 0>;