Lines Matching +full:mbox +full:- +full:cells
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
18 #include "mec172x/mec172x-vw-routing.dtsi"
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-m4";
29 cpu-power-states = <&idle &suspend_to_ram>;
32 power-states {
34 compatible = "zephyr,power-state";
35 power-state-name = "suspend-to-idle";
36 min-residency-us = <1000000>;
40 compatible = "zephyr,power-state";
41 power-state-name = "suspend-to-ram";
42 min-residency-us = <2000000>;
52 compatible = "mmio-sram";
61 compatible = "microchip,xec-pcr";
63 reg-names = "pcrr", "vbatr";
65 core-clock-div = <1>;
67 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
68 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
69 clk32kmon-period-min = <1435>;
70 clk32kmon-period-max = <1495>;
71 clk32kmon-duty-cycle-var-max = <132>;
72 clk32kmon-valid-min = <4>;
73 xtal-enable-delay-ms = <300>;
74 pll-lock-timeout-ms = <30>;
76 pinctrl-0 = <&clk_32khz_in_gpio165>;
77 pinctrl-names = "default";
78 #clock-cells = <3>;
81 compatible = "microchip,xec-ecia";
83 direct-capable-girqs = <13 14 15 16 17 18 19 20 21 23>;
85 #address-cells = <1>;
86 #size-cells = <1>;
91 compatible = "microchip,xec-ecia-girq";
94 girq-id = <0>;
102 compatible = "microchip,xec-ecia-girq";
105 girq-id = <1>;
113 compatible = "microchip,xec-ecia-girq";
116 girq-id = <2>;
124 compatible = "microchip,xec-ecia-girq";
127 girq-id = <3>;
135 compatible = "microchip,xec-ecia-girq";
138 girq-id = <4>;
146 compatible = "microchip,xec-ecia-girq";
149 girq-id = <5>;
154 compatible = "microchip,xec-ecia-girq";
157 girq-id = <6>;
163 compatible = "microchip,xec-ecia-girq";
166 girq-id = <7>;
173 compatible = "microchip,xec-ecia-girq";
176 girq-id = <8>;
181 compatible = "microchip,xec-ecia-girq";
184 girq-id = <9>;
190 compatible = "microchip,xec-ecia-girq";
193 girq-id = <10>;
200 compatible = "microchip,xec-ecia-girq";
203 girq-id = <11>;
208 compatible = "microchip,xec-ecia-girq";
211 girq-id = <12>;
216 compatible = "microchip,xec-ecia-girq";
219 girq-id = <13>;
225 compatible = "microchip,xec-ecia-girq";
228 girq-id = <14>;
233 compatible = "microchip,xec-ecia-girq";
236 girq-id = <15>;
241 compatible = "microchip,xec-ecia-girq";
244 girq-id = <16>;
251 compatible = "microchip,xec-ecia-girq";
254 girq-id = <17>;
260 compatible = "microchip,xec-ecia-girq";
263 girq-id = <18>;
268 pinctrl: pin-controller@40081000 {
269 compatible = "microchip,xec-pinctrl";
270 #address-cells = <1>;
271 #size-cells = <1>;
275 compatible = "microchip,xec-gpio-v2";
279 gpio-controller;
280 port-id = <0>;
281 girq-id = <11>;
282 #gpio-cells=<2>;
285 compatible = "microchip,xec-gpio-v2";
289 gpio-controller;
290 port-id = <1>;
291 girq-id = <10>;
292 #gpio-cells=<2>;
295 compatible = "microchip,xec-gpio-v2";
298 gpio-controller;
300 port-id = <2>;
301 girq-id = <9>;
302 #gpio-cells=<2>;
305 compatible = "microchip,xec-gpio-v2";
308 gpio-controller;
310 port-id = <3>;
311 girq-id = <8>;
312 #gpio-cells=<2>;
315 compatible = "microchip,xec-gpio-v2";
318 gpio-controller;
320 port-id = <4>;
321 girq-id = <12>;
322 #gpio-cells=<2>;
325 compatible = "microchip,xec-gpio-v2";
328 gpio-controller;
330 port-id = <5>;
331 girq-id = <26>;
332 #gpio-cells=<2>;
336 compatible = "microchip,xec-watchdog";
343 compatible = "microchip,xec-rtos-timer";
349 compatible = "microchip,xec-timer";
350 clock-frequency = <48000000>;
355 max-value = <0xFFFF>;
360 compatible = "microchip,xec-timer";
361 clock-frequency = <48000000>;
366 max-value = <0xFFFF>;
371 compatible = "microchip,xec-timer";
372 clock-frequency = <48000000>;
377 max-value = <0xFFFF>;
382 compatible = "microchip,xec-timer";
383 clock-frequency = <48000000>;
388 max-value = <0xFFFF>;
398 compatible = "microchip,xec-timer";
399 clock-frequency = <48000000>;
404 max-value = <0xFFFFFFFF>;
409 compatible = "microchip,xec-timer";
410 clock-frequency = <48000000>;
415 max-value = <0xFFFFFFFF>;
474 bbram: bb-ram@4000a800 {
475 compatible = "microchip,xec-bbram";
477 reg-names = "memory";
487 compatible = "microchip,xec-dmac";
510 #dma-cells = <2>;
511 dma-channels = <16>;
512 dma-requests = <16>;
516 compatible = "microchip,xec-eeprom";
525 compatible = "microchip,xec-i2c-v2";
527 clock-frequency = <I2C_BITRATE_STANDARD>;
531 #address-cells = <1>;
532 #size-cells = <0>;
536 compatible = "microchip,xec-i2c-v2";
538 clock-frequency = <I2C_BITRATE_STANDARD>;
542 #address-cells = <1>;
543 #size-cells = <0>;
547 compatible = "microchip,xec-i2c-v2";
549 clock-frequency = <I2C_BITRATE_STANDARD>;
553 #address-cells = <1>;
554 #size-cells = <0>;
558 compatible = "microchip,xec-i2c-v2";
560 clock-frequency = <I2C_BITRATE_STANDARD>;
564 #address-cells = <1>;
565 #size-cells = <0>;
569 compatible = "microchip,xec-i2c-v2";
571 clock-frequency = <I2C_BITRATE_STANDARD>;
575 #address-cells = <1>;
576 #size-cells = <0>;
580 compatible = "microchip,xec-ps2";
585 #address-cells = <1>;
586 #size-cells = <0>;
590 compatible = "microchip,xec-pwm";
594 #pwm-cells = <3>;
597 compatible = "microchip,xec-pwm";
601 #pwm-cells = <3>;
604 compatible = "microchip,xec-pwm";
608 #pwm-cells = <3>;
611 compatible = "microchip,xec-pwm";
615 #pwm-cells = <3>;
618 compatible = "microchip,xec-pwm";
622 #pwm-cells = <3>;
625 compatible = "microchip,xec-pwm";
629 #pwm-cells = <3>;
632 compatible = "microchip,xec-pwm";
636 #pwm-cells = <3>;
639 compatible = "microchip,xec-pwm";
643 #pwm-cells = <3>;
646 compatible = "microchip,xec-pwm";
650 #pwm-cells = <3>;
653 compatible = "microchip,xec-tach";
658 #address-cells = <1>;
659 #size-cells = <0>;
663 compatible = "microchip,xec-tach";
668 #address-cells = <1>;
669 #size-cells = <0>;
673 compatible = "microchip,xec-tach";
678 #address-cells = <1>;
679 #size-cells = <0>;
683 compatible = "microchip,xec-tach";
688 #address-cells = <1>;
689 #size-cells = <0>;
707 compatible = "microchip,xec-adc";
713 #io-channel-cells = <1>;
717 compatible = "microchip,xec-kscan";
723 #address-cells = <1>;
724 #size-cells = <0>;
727 compatible = "microchip,xec-peci";
732 #address-cells = <1>;
733 #size-cells = <0>;
740 clock-frequency = <12000000>;
742 chip-select = <0>;
743 #address-cells = <1>;
744 #size-cells = <0>;
842 compatible = "microchip,xec-uart";
845 clock-frequency = <1843200>;
846 current-speed = <38400>;
853 compatible = "microchip,xec-uart";
856 clock-frequency = <1843200>;
857 current-speed = <38400>;
864 compatible = "microchip,xec-espi-v2";
865 /* reg tuple contains one 32-bit address cell and one
866 * 32-bit length(size) cell.
868 #address-cells = <1>;
869 #size-cells = <1>;
873 reg-names = "io", "mem", "vw";
877 interrupt-names = "pc", "bm1", "bm2", "ltr", "oob_up",
892 compatible = "microchip,xec-espi-saf-v2";
895 reg-names = "safbr", "safqspi", "safcomm";
897 interrupt-names = "done", "err";
904 mbox0: mbox@400f0000 {
905 compatible = "microchip,xec-espi-host-dev";
914 compatible = "microchip,xec-espi-host-dev";
917 interrupt-names = "kbc_obe", "kbc_ibf";
924 compatible = "microchip,xec-espi-host-dev";
927 interrupt-names = "acpi_ibf", "acpi_obe";
934 compatible = "microchip,xec-espi-host-dev";
937 interrupt-names = "acpi_ibf", "acpi_obe";
944 compatible = "microchip,xec-espi-host-dev";
947 interrupt-names = "acpi_ibf", "acpi_obe";
954 compatible = "microchip,xec-espi-host-dev";
957 interrupt-names = "acpi_ibf", "acpi_obe";
964 compatible = "microchip,xec-espi-host-dev";
967 interrupt-names = "acpi_ibf", "acpi_obe";
974 compatible = "microchip,xec-espi-host-dev";
977 interrupt-names = "pm1_ctl", "pm1_en", "pm1_sts";
985 compatible = "microchip,xec-espi-host-dev";
991 compatible = "microchip,xec-espi-host-dev";
999 compatible = "microchip,xec-espi-host-dev";
1007 compatible = "microchip,xec-espi-host-dev";
1015 compatible = "microchip,xec-espi-host-dev";
1024 /* Capture writes to host I/O 0x80 - 0x83 */
1026 compatible = "microchip,xec-espi-host-dev";
1034 /* Capture writes to an 8-bit I/O and map to one of 0x80 to 0x83 */
1036 compatible = "microchip,xec-espi-host-dev";
1039 host-io = <0x90>;
1041 host-io-addr-mask = <0x01>;
1047 compatible = "microchip,xec-symcr";
1053 #address-cells = <1>;
1054 #size-cells = <1>;
1065 arm,num-irq-priority-bits = <3>;