Lines Matching +full:pinmux +full:- +full:cells
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
15 zephyr,flash-controller = &nvmctrl;
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-m4f";
26 #address-cells = <1>;
27 #size-cells = <1>;
30 compatible = "arm,armv7m-mpu";
32 arm,num-mpu-regions = <8>;
38 adc-0 = &adc0;
39 adc-1 = &adc1;
41 port-a = &porta;
42 port-b = &portb;
43 port-c = &portc;
44 port-d = &portd;
46 sercom-0 = &sercom0;
47 sercom-1 = &sercom1;
48 sercom-2 = &sercom2;
49 sercom-3 = &sercom3;
50 sercom-4 = &sercom4;
51 sercom-5 = &sercom5;
52 sercom-6 = &sercom6;
53 sercom-7 = &sercom7;
55 tc-0 = &tc0;
56 tc-2 = &tc2;
57 tc-4 = &tc4;
58 tc-6 = &tc6;
60 tcc-0 = &tcc0;
61 tcc-1 = &tcc1;
62 tcc-2 = &tcc2;
63 tcc-3 = &tcc3;
64 tcc-4 = &tcc4;
75 compatible = "mmio-sram";
80 compatible = "mmio-sram";
85 compatible = "atmel,sam0-id";
93 compatible = "atmel,samd5x-mclk";
95 #clock-cells = <2>;
99 compatible = "atmel,samd5x-gclk";
101 #clock-cells = <1>;
105 compatible = "atmel,sam0-nvmctrl";
108 lock-regions = <32>;
110 #address-cells = <1>;
111 #size-cells = <1>;
114 compatible = "soc-nv-flash";
115 write-block-size = <8>;
120 compatible = "atmel,sam0-dmac";
123 #dma-cells = <2>;
127 compatible = "atmel,sam0-eic";
135 pinmux_a: pinmux@41008000 {
136 compatible = "atmel,sam0-pinmux";
140 pinmux_b: pinmux@41008080 {
141 compatible = "atmel,sam0-pinmux";
145 pinmux_c: pinmux@41008100 {
146 compatible = "atmel,sam0-pinmux";
150 pinmux_d: pinmux@41008180 {
151 compatible = "atmel,sam0-pinmux";
156 compatible = "atmel,sam0-watchdog";
162 compatible = "atmel,sam0-sercom";
167 clock-names = "GCLK", "MCLK";
171 compatible = "atmel,sam0-sercom";
176 clock-names = "GCLK", "MCLK";
180 compatible = "atmel,sam0-sercom";
185 clock-names = "GCLK", "MCLK";
189 compatible = "atmel,sam0-sercom";
194 clock-names = "GCLK", "MCLK";
198 compatible = "atmel,sam0-sercom";
203 clock-names = "GCLK", "MCLK";
207 compatible = "atmel,sam0-sercom";
212 clock-names = "GCLK", "MCLK";
216 compatible = "atmel,sam0-sercom";
221 clock-names = "GCLK", "MCLK";
225 compatible = "atmel,sam0-sercom";
230 clock-names = "GCLK", "MCLK";
234 compatible = "atmel,sam0-pinctrl";
235 #address-cells = <1>;
236 #size-cells = <1>;
240 compatible = "atmel,sam0-gpio";
242 gpio-controller;
243 #gpio-cells = <2>;
244 #atmel,pin-cells = <2>;
248 compatible = "atmel,sam0-gpio";
250 gpio-controller;
251 #gpio-cells = <2>;
252 #atmel,pin-cells = <2>;
256 compatible = "atmel,sam0-gpio";
258 gpio-controller;
259 #gpio-cells = <2>;
260 #atmel,pin-cells = <2>;
264 compatible = "atmel,sam0-gpio";
266 gpio-controller;
267 #gpio-cells = <2>;
268 #atmel,pin-cells = <2>;
273 compatible = "atmel,sam0-usb";
277 num-bidir-endpoints = <8>;
281 compatible = "atmel,sam-trng";
287 compatible = "atmel,sam0-rtc";
290 clock-generator = <0>;
295 compatible = "atmel,sam0-adc";
298 interrupt-names = "overrun", "resrdy";
302 * - table 54-8, section 54.6, page 2020
303 * - table 54-24, section 54.10.4, page 2031
304 * -> 48 MHz GCLK(2) / 4 = 12 MHz
308 #io-channel-cells = <1>;
310 clock-names = "GCLK", "MCLK";
311 calib-offset = <0>;
315 compatible = "atmel,sam0-adc";
318 interrupt-names = "overrun", "resrdy";
322 * - table 54-8, section 54.6, page 2020
323 * - table 54-24, section 54.10.4, page 2031
324 * -> 48 MHz GCLK(2) / 4 = 12 MHz
328 #io-channel-cells = <1>;
330 clock-names = "GCLK", "MCLK";
331 calib-offset = <14>;
335 compatible = "atmel,sam0-tc32";
339 clock-names = "GCLK", "MCLK";
343 compatible = "atmel,sam0-tc32";
347 clock-names = "GCLK", "MCLK";
351 compatible = "atmel,sam0-tc32";
355 clock-names = "GCLK", "MCLK";
359 compatible = "atmel,sam0-tc32";
363 clock-names = "GCLK", "MCLK";
367 compatible = "atmel,sam0-tcc";
372 clock-names = "GCLK", "MCLK";
374 counter-size = <24>;
378 compatible = "atmel,sam0-tcc";
382 clock-names = "GCLK", "MCLK";
384 counter-size = <24>;
388 compatible = "atmel,sam0-tcc";
392 clock-names = "GCLK", "MCLK";
394 counter-size = <16>;
398 compatible = "atmel,sam0-tcc";
402 clock-names = "GCLK", "MCLK";
404 counter-size = <16>;
408 compatible = "atmel,sam0-tcc";
412 clock-names = "GCLK", "MCLK";
414 counter-size = <16>;
420 arm,num-irq-priority-bits = <3>;