Lines Matching +full:wakeup +full:- +full:line
2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
5 * SPDX-License-Identifier: Apache-2.0
94 struct uart_stm32_data *data = dev->data; in uart_stm32_pm_policy_state_lock_get()
96 if (!data->pm_policy_state_on) { in uart_stm32_pm_policy_state_lock_get()
97 data->pm_policy_state_on = true; in uart_stm32_pm_policy_state_lock_get()
104 struct uart_stm32_data *data = dev->data; in uart_stm32_pm_policy_state_lock_put()
106 if (data->pm_policy_state_on) { in uart_stm32_pm_policy_state_lock_put()
107 data->pm_policy_state_on = false; in uart_stm32_pm_policy_state_lock_put()
115 const struct uart_stm32_config *config = dev->config; in uart_stm32_set_baudrate()
116 struct uart_stm32_data *data = dev->data; in uart_stm32_set_baudrate()
121 if (IS_ENABLED(STM32_UART_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) { in uart_stm32_set_baudrate()
122 if (clock_control_get_rate(data->clock, in uart_stm32_set_baudrate()
123 (clock_control_subsys_t)&config->pclken[1], in uart_stm32_set_baudrate()
129 if (clock_control_get_rate(data->clock, in uart_stm32_set_baudrate()
130 (clock_control_subsys_t)&config->pclken[0], in uart_stm32_set_baudrate()
138 if (IS_LPUART_INSTANCE(config->usart)) { in uart_stm32_set_baudrate()
152 LOG_ERR("Unable to set %s to %d", dev->name, baud_rate); in uart_stm32_set_baudrate()
158 LL_LPUART_SetPrescaler(config->usart, presc_val); in uart_stm32_set_baudrate()
162 LOG_ERR("Unable to set %s to %d", dev->name, baud_rate); in uart_stm32_set_baudrate()
166 LL_LPUART_SetBaudRate(config->usart, in uart_stm32_set_baudrate()
173 __ASSERT(LL_LPUART_ReadReg(config->usart, BRR) >= 0x300U, in uart_stm32_set_baudrate()
177 __ASSERT(LL_LPUART_ReadReg(config->usart, BRR) < 0x000FFFFFU, in uart_stm32_set_baudrate()
182 LL_USART_SetOverSampling(config->usart, in uart_stm32_set_baudrate()
185 LL_USART_SetBaudRate(config->usart, in uart_stm32_set_baudrate()
195 __ASSERT(LL_USART_ReadReg(config->usart, BRR) >= 16, in uart_stm32_set_baudrate()
206 const struct uart_stm32_config *config = dev->config; in uart_stm32_set_parity()
208 LL_USART_SetParity(config->usart, parity); in uart_stm32_set_parity()
213 const struct uart_stm32_config *config = dev->config; in uart_stm32_get_parity()
215 return LL_USART_GetParity(config->usart); in uart_stm32_get_parity()
221 const struct uart_stm32_config *config = dev->config; in uart_stm32_set_stopbits()
223 LL_USART_SetStopBitsLength(config->usart, stopbits); in uart_stm32_set_stopbits()
228 const struct uart_stm32_config *config = dev->config; in uart_stm32_get_stopbits()
230 return LL_USART_GetStopBitsLength(config->usart); in uart_stm32_get_stopbits()
236 const struct uart_stm32_config *config = dev->config; in uart_stm32_set_databits()
238 LL_USART_SetDataWidth(config->usart, databits); in uart_stm32_set_databits()
243 const struct uart_stm32_config *config = dev->config; in uart_stm32_get_databits()
245 return LL_USART_GetDataWidth(config->usart); in uart_stm32_get_databits()
251 const struct uart_stm32_config *config = dev->config; in uart_stm32_set_hwctrl()
253 LL_USART_SetHWFlowCtrl(config->usart, hwctrl); in uart_stm32_set_hwctrl()
258 const struct uart_stm32_config *config = dev->config; in uart_stm32_get_hwctrl()
260 return LL_USART_GetHWFlowCtrl(config->usart); in uart_stm32_get_hwctrl()
267 const struct uart_stm32_config *config = dev->config; in uart_stm32_set_driver_enable()
270 LL_USART_EnableDEMode(config->usart); in uart_stm32_set_driver_enable()
272 LL_USART_DisableDEMode(config->usart); in uart_stm32_set_driver_enable()
278 const struct uart_stm32_config *config = dev->config; in uart_stm32_get_driver_enable()
280 return LL_USART_IsEnabledDEMode(config->usart); in uart_stm32_get_driver_enable()
318 if (IS_LPUART_INSTANCE(config->usart)) { in uart_stm32_cfg2ll_stopbits()
331 if (IS_LPUART_INSTANCE(config->usart)) { in uart_stm32_cfg2ll_stopbits()
464 const struct uart_stm32_config *config = dev->config; in uart_stm32_parameters_set()
465 struct uart_stm32_data *data = dev->data; in uart_stm32_parameters_set()
466 struct uart_config *uart_cfg = data->uart_cfg; in uart_stm32_parameters_set()
467 const uint32_t parity = uart_stm32_cfg2ll_parity(cfg->parity); in uart_stm32_parameters_set()
468 const uint32_t stopbits = uart_stm32_cfg2ll_stopbits(config, cfg->stop_bits); in uart_stm32_parameters_set()
469 const uint32_t databits = uart_stm32_cfg2ll_databits(cfg->data_bits, in uart_stm32_parameters_set()
470 cfg->parity); in uart_stm32_parameters_set()
471 const uint32_t flowctrl = uart_stm32_cfg2ll_hwctrl(cfg->flow_ctrl); in uart_stm32_parameters_set()
473 bool driver_enable = cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RS485; in uart_stm32_parameters_set()
477 /* Called via (re-)init function, so the SoC either just booted, in uart_stm32_parameters_set()
478 * or is returning from a low-power state where it lost register in uart_stm32_parameters_set()
481 LL_USART_ConfigCharacter(config->usart, in uart_stm32_parameters_set()
486 uart_stm32_set_baudrate(dev, cfg->baudrate); in uart_stm32_parameters_set()
511 if (cfg->baudrate != uart_cfg->baudrate) { in uart_stm32_parameters_set()
512 uart_stm32_set_baudrate(dev, cfg->baudrate); in uart_stm32_parameters_set()
513 uart_cfg->baudrate = cfg->baudrate; in uart_stm32_parameters_set()
522 const struct uart_stm32_config *config = dev->config; in uart_stm32_configure()
523 struct uart_stm32_data *data = dev->data; in uart_stm32_configure()
524 struct uart_config *uart_cfg = data->uart_cfg; in uart_stm32_configure()
525 const uint32_t parity = uart_stm32_cfg2ll_parity(cfg->parity); in uart_stm32_configure()
526 const uint32_t stopbits = uart_stm32_cfg2ll_stopbits(config, cfg->stop_bits); in uart_stm32_configure()
527 const uint32_t databits = uart_stm32_cfg2ll_databits(cfg->data_bits, in uart_stm32_configure()
528 cfg->parity); in uart_stm32_configure()
531 if ((cfg->parity == UART_CFG_PARITY_MARK) || in uart_stm32_configure()
532 (cfg->parity == UART_CFG_PARITY_SPACE)) { in uart_stm32_configure()
533 return -ENOTSUP; in uart_stm32_configure()
537 if ((cfg->parity != UART_CFG_PARITY_NONE) && in uart_stm32_configure()
538 (cfg->data_bits == UART_CFG_DATA_BITS_9)) { in uart_stm32_configure()
539 return -ENOTSUP; in uart_stm32_configure()
545 if (uart_stm32_ll2cfg_stopbits(stopbits) != cfg->stop_bits) { in uart_stm32_configure()
546 return -ENOTSUP; in uart_stm32_configure()
552 if (uart_stm32_ll2cfg_databits(databits, parity) != cfg->data_bits) { in uart_stm32_configure()
553 return -ENOTSUP; in uart_stm32_configure()
557 if (!(cfg->flow_ctrl == UART_CFG_FLOW_CTRL_NONE in uart_stm32_configure()
558 || (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS && in uart_stm32_configure()
559 IS_UART_HWFLOW_INSTANCE(config->usart)) in uart_stm32_configure()
561 || (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RS485 && in uart_stm32_configure()
562 IS_UART_DRIVER_ENABLE_INSTANCE(config->usart)) in uart_stm32_configure()
565 return -ENOTSUP; in uart_stm32_configure()
568 LL_USART_Disable(config->usart); in uart_stm32_configure()
570 /* Set basic parmeters, such as data-/stop-bit, parity, and baudrate */ in uart_stm32_configure()
573 LL_USART_Enable(config->usart); in uart_stm32_configure()
575 /* Upon successful configuration, persist the syscall-passed in uart_stm32_configure()
577 * This allows restoring it, should the device return from a low-power in uart_stm32_configure()
588 struct uart_stm32_data *data = dev->data; in uart_stm32_config_get()
589 struct uart_config *uart_cfg = data->uart_cfg; in uart_stm32_config_get()
591 cfg->baudrate = uart_cfg->baudrate; in uart_stm32_config_get()
592 cfg->parity = uart_stm32_ll2cfg_parity(uart_stm32_get_parity(dev)); in uart_stm32_config_get()
593 cfg->stop_bits = uart_stm32_ll2cfg_stopbits( in uart_stm32_config_get()
595 cfg->data_bits = uart_stm32_ll2cfg_databits( in uart_stm32_config_get()
597 cfg->flow_ctrl = uart_stm32_ll2cfg_hwctrl( in uart_stm32_config_get()
601 cfg->flow_ctrl = UART_CFG_FLOW_CTRL_RS485; in uart_stm32_config_get()
614 const struct uart_stm32_config *config = dev->config; in uart_stm32_poll_in_visitor()
617 if (LL_USART_IsActiveFlag_ORE(config->usart)) { in uart_stm32_poll_in_visitor()
618 LL_USART_ClearFlag_ORE(config->usart); in uart_stm32_poll_in_visitor()
625 if (!LL_USART_IsActiveFlag_RXNE(config->usart)) { in uart_stm32_poll_in_visitor()
626 return -1; in uart_stm32_poll_in_visitor()
639 const struct uart_stm32_config *config = dev->config; in uart_stm32_poll_out_visitor()
641 struct uart_stm32_data *data = dev->data; in uart_stm32_poll_out_visitor()
651 if (LL_USART_IsActiveFlag_TXE(config->usart)) { in uart_stm32_poll_out_visitor()
653 if (LL_USART_IsActiveFlag_TXE(config->usart)) { in uart_stm32_poll_out_visitor()
665 if (!data->tx_poll_stream_on && !data->tx_int_stream_on) { in uart_stm32_poll_out_visitor()
666 data->tx_poll_stream_on = true; in uart_stm32_poll_out_visitor()
676 LL_USART_EnableIT_TC(config->usart); in uart_stm32_poll_out_visitor()
686 *((unsigned char *)in) = (unsigned char)LL_USART_ReceiveData8(config->usart); in poll_in_u8()
691 LL_USART_TransmitData8(config->usart, *((uint8_t *)out)); in poll_out_u8()
708 LL_USART_TransmitData9(config->usart, *((uint16_t *)out)); in poll_out_u9()
713 *((uint16_t *)in) = LL_USART_ReceiveData9(config->usart); in poll_in_u9()
730 const struct uart_stm32_config *config = dev->config; in uart_stm32_err_check()
738 if (LL_USART_IsActiveFlag_ORE(config->usart)) { in uart_stm32_err_check()
742 if (LL_USART_IsActiveFlag_PE(config->usart)) { in uart_stm32_err_check()
746 if (LL_USART_IsActiveFlag_FE(config->usart)) { in uart_stm32_err_check()
750 if (LL_USART_IsActiveFlag_NE(config->usart)) { in uart_stm32_err_check()
755 if (LL_USART_IsActiveFlag_LBD(config->usart)) { in uart_stm32_err_check()
760 LL_USART_ClearFlag_LBD(config->usart); in uart_stm32_err_check()
766 * --> so is the RXNE flag also cleared ! in uart_stm32_err_check()
769 LL_USART_ClearFlag_ORE(config->usart); in uart_stm32_err_check()
773 LL_USART_ClearFlag_PE(config->usart); in uart_stm32_err_check()
777 LL_USART_ClearFlag_FE(config->usart); in uart_stm32_err_check()
781 LL_USART_ClearFlag_NE(config->usart); in uart_stm32_err_check()
789 struct uart_stm32_data *data = dev->data; in __uart_stm32_get_clock()
792 data->clock = clk; in __uart_stm32_get_clock()
803 const struct uart_stm32_config *config = dev->config; in uart_stm32_fifo_fill_visitor()
807 if (!LL_USART_IsActiveFlag_TXE(config->usart)) { in uart_stm32_fifo_fill_visitor()
814 while ((size - num_tx > 0) && LL_USART_IsActiveFlag_TXE(config->usart)) { in uart_stm32_fifo_fill_visitor()
832 LL_USART_TransmitData8(config->usart, data[offset]); in fifo_fill_with_u8()
839 return -ENOTSUP; in uart_stm32_fifo_fill()
851 const struct uart_stm32_config *config = dev->config; in uart_stm32_fifo_read_visitor()
854 while ((size - num_rx > 0) && LL_USART_IsActiveFlag_RXNE(config->usart)) { in uart_stm32_fifo_read_visitor()
861 if (LL_USART_IsActiveFlag_ORE(config->usart)) { in uart_stm32_fifo_read_visitor()
862 LL_USART_ClearFlag_ORE(config->usart); in uart_stm32_fifo_read_visitor()
878 data[offset] = LL_USART_ReceiveData8(config->usart); in fifo_read_with_u8()
885 return -ENOTSUP; in uart_stm32_fifo_read()
899 LL_USART_TransmitData9(config->usart, data[offset]); in fifo_fill_with_u16()
906 return -ENOTSUP; in uart_stm32_fifo_fill_u16()
917 data[offset] = LL_USART_ReceiveData9(config->usart); in fifo_read_with_u16()
924 return -ENOTSUP; in uart_stm32_fifo_read_u16()
934 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_tx_enable()
936 struct uart_stm32_data *data = dev->data; in uart_stm32_irq_tx_enable()
942 data->tx_poll_stream_on = false; in uart_stm32_irq_tx_enable()
943 data->tx_int_stream_on = true; in uart_stm32_irq_tx_enable()
946 LL_USART_EnableIT_TC(config->usart); in uart_stm32_irq_tx_enable()
955 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_tx_disable()
957 struct uart_stm32_data *data = dev->data; in uart_stm32_irq_tx_disable()
963 LL_USART_DisableIT_TC(config->usart); in uart_stm32_irq_tx_disable()
966 data->tx_int_stream_on = false; in uart_stm32_irq_tx_disable()
977 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_tx_ready()
979 return LL_USART_IsActiveFlag_TXE(config->usart) && in uart_stm32_irq_tx_ready()
980 LL_USART_IsEnabledIT_TC(config->usart); in uart_stm32_irq_tx_ready()
985 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_tx_complete()
987 return LL_USART_IsActiveFlag_TC(config->usart); in uart_stm32_irq_tx_complete()
992 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_rx_enable()
994 LL_USART_EnableIT_RXNE(config->usart); in uart_stm32_irq_rx_enable()
999 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_rx_disable()
1001 LL_USART_DisableIT_RXNE(config->usart); in uart_stm32_irq_rx_disable()
1006 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_rx_ready()
1011 return LL_USART_IsActiveFlag_RXNE(config->usart); in uart_stm32_irq_rx_ready()
1016 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_err_enable()
1019 LL_USART_EnableIT_ERROR(config->usart); in uart_stm32_irq_err_enable()
1021 /* Enable Line break detection */ in uart_stm32_irq_err_enable()
1022 if (IS_UART_LIN_INSTANCE(config->usart)) { in uart_stm32_irq_err_enable()
1023 LL_USART_EnableIT_LBD(config->usart); in uart_stm32_irq_err_enable()
1027 LL_USART_EnableIT_PE(config->usart); in uart_stm32_irq_err_enable()
1032 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_err_disable()
1035 LL_USART_DisableIT_ERROR(config->usart); in uart_stm32_irq_err_disable()
1037 /* Disable Line break detection */ in uart_stm32_irq_err_disable()
1038 if (IS_UART_LIN_INSTANCE(config->usart)) { in uart_stm32_irq_err_disable()
1039 LL_USART_DisableIT_LBD(config->usart); in uart_stm32_irq_err_disable()
1043 LL_USART_DisableIT_PE(config->usart); in uart_stm32_irq_err_disable()
1048 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_is_pending()
1050 return ((LL_USART_IsActiveFlag_RXNE(config->usart) && in uart_stm32_irq_is_pending()
1051 LL_USART_IsEnabledIT_RXNE(config->usart)) || in uart_stm32_irq_is_pending()
1052 (LL_USART_IsActiveFlag_TC(config->usart) && in uart_stm32_irq_is_pending()
1053 LL_USART_IsEnabledIT_TC(config->usart))); in uart_stm32_irq_is_pending()
1065 struct uart_stm32_data *data = dev->data; in uart_stm32_irq_callback_set()
1067 data->user_cb = cb; in uart_stm32_irq_callback_set()
1068 data->user_data = cb_data; in uart_stm32_irq_callback_set()
1071 data->async_cb = NULL; in uart_stm32_irq_callback_set()
1072 data->async_user_data = NULL; in uart_stm32_irq_callback_set()
1083 if (data->async_cb) { in async_user_callback()
1084 data->async_cb(data->uart_dev, event, data->async_user_data); in async_user_callback()
1090 LOG_DBG("rx_rdy: (%d %d)", data->dma_rx.offset, data->dma_rx.counter); in async_evt_rx_rdy()
1094 .data.rx.buf = data->dma_rx.buffer, in async_evt_rx_rdy()
1095 .data.rx.len = data->dma_rx.counter - data->dma_rx.offset, in async_evt_rx_rdy()
1096 .data.rx.offset = data->dma_rx.offset in async_evt_rx_rdy()
1100 data->dma_rx.offset = data->dma_rx.counter; in async_evt_rx_rdy()
1115 .data.rx_stop.data.len = data->dma_rx.counter, in async_evt_rx_err()
1117 .data.rx_stop.data.buf = data->dma_rx.buffer in async_evt_rx_err()
1125 LOG_DBG("tx done: %d", data->dma_tx.counter); in async_evt_tx_done()
1129 .data.tx.buf = data->dma_tx.buffer, in async_evt_tx_done()
1130 .data.tx.len = data->dma_tx.counter in async_evt_tx_done()
1134 data->dma_tx.buffer_length = 0; in async_evt_tx_done()
1135 data->dma_tx.counter = 0; in async_evt_tx_done()
1142 LOG_DBG("tx abort: %d", data->dma_tx.counter); in async_evt_tx_abort()
1146 .data.tx.buf = data->dma_tx.buffer, in async_evt_tx_abort()
1147 .data.tx.len = data->dma_tx.counter in async_evt_tx_abort()
1151 data->dma_tx.buffer_length = 0; in async_evt_tx_abort()
1152 data->dma_tx.counter = 0; in async_evt_tx_abort()
1170 .data.rx_buf.buf = data->dma_rx.buffer, in async_evt_rx_buf_release()
1189 struct uart_stm32_data *data = dev->data; in uart_stm32_dma_rx_flush()
1191 if (dma_get_status(data->dma_rx.dma_dev, in uart_stm32_dma_rx_flush()
1192 data->dma_rx.dma_channel, &stat) == 0) { in uart_stm32_dma_rx_flush()
1193 size_t rx_rcv_len = data->dma_rx.buffer_length - in uart_stm32_dma_rx_flush()
1195 if (rx_rcv_len > data->dma_rx.offset) { in uart_stm32_dma_rx_flush()
1196 data->dma_rx.counter = rx_rcv_len; in uart_stm32_dma_rx_flush()
1211 struct uart_stm32_data *data = dev->data; in uart_stm32_isr()
1213 const struct uart_stm32_config *config = dev->config; in uart_stm32_isr()
1217 if (LL_USART_IsEnabledIT_TC(config->usart) && in uart_stm32_isr()
1218 LL_USART_IsActiveFlag_TC(config->usart)) { in uart_stm32_isr()
1220 if (data->tx_poll_stream_on) { in uart_stm32_isr()
1224 LL_USART_DisableIT_TC(config->usart); in uart_stm32_isr()
1225 data->tx_poll_stream_on = false; in uart_stm32_isr()
1236 if (data->user_cb) { in uart_stm32_isr()
1237 data->user_cb(dev, data->user_data); in uart_stm32_isr()
1242 if (LL_USART_IsEnabledIT_IDLE(config->usart) && in uart_stm32_isr()
1243 LL_USART_IsActiveFlag_IDLE(config->usart)) { in uart_stm32_isr()
1245 LL_USART_ClearFlag_IDLE(config->usart); in uart_stm32_isr()
1249 if (data->dma_rx.timeout == 0) { in uart_stm32_isr()
1253 async_timer_start(&data->dma_rx.timeout_work, in uart_stm32_isr()
1254 data->dma_rx.timeout); in uart_stm32_isr()
1256 } else if (LL_USART_IsEnabledIT_TC(config->usart) && in uart_stm32_isr()
1257 LL_USART_IsActiveFlag_TC(config->usart)) { in uart_stm32_isr()
1259 LL_USART_DisableIT_TC(config->usart); in uart_stm32_isr()
1260 LL_USART_ClearFlag_TC(config->usart); in uart_stm32_isr()
1267 } else if (LL_USART_IsEnabledIT_RXNE(config->usart) && in uart_stm32_isr()
1268 LL_USART_IsActiveFlag_RXNE(config->usart)) { in uart_stm32_isr()
1271 LL_USART_ClearFlag_RXNE(config->usart); in uart_stm32_isr()
1274 LL_USART_RequestRxDataFlush(config->usart); in uart_stm32_isr()
1290 struct uart_stm32_data *data = dev->data; in uart_stm32_async_callback_set()
1292 data->async_cb = callback; in uart_stm32_async_callback_set()
1293 data->async_user_data = user_data; in uart_stm32_async_callback_set()
1296 data->user_cb = NULL; in uart_stm32_async_callback_set()
1297 data->user_data = NULL; in uart_stm32_async_callback_set()
1305 const struct uart_stm32_config *config = dev->config; in uart_stm32_dma_tx_enable()
1307 LL_USART_EnableDMAReq_TX(config->usart); in uart_stm32_dma_tx_enable()
1321 const struct uart_stm32_config *config = dev->config; in uart_stm32_dma_tx_disable()
1323 LL_USART_DisableDMAReq_TX(config->usart); in uart_stm32_dma_tx_disable()
1329 const struct uart_stm32_config *config = dev->config; in uart_stm32_dma_rx_enable()
1330 struct uart_stm32_data *data = dev->data; in uart_stm32_dma_rx_enable()
1332 LL_USART_EnableDMAReq_RX(config->usart); in uart_stm32_dma_rx_enable()
1334 data->dma_rx.enabled = true; in uart_stm32_dma_rx_enable()
1339 struct uart_stm32_data *data = dev->data; in uart_stm32_dma_rx_disable()
1341 data->dma_rx.enabled = false; in uart_stm32_dma_rx_disable()
1346 const struct uart_stm32_config *config = dev->config; in uart_stm32_async_rx_disable()
1347 struct uart_stm32_data *data = dev->data; in uart_stm32_async_rx_disable()
1352 if (!data->dma_rx.enabled) { in uart_stm32_async_rx_disable()
1354 return -EFAULT; in uart_stm32_async_rx_disable()
1357 LL_USART_DisableIT_IDLE(config->usart); in uart_stm32_async_rx_disable()
1365 (void)k_work_cancel_delayable(&data->dma_rx.timeout_work); in uart_stm32_async_rx_disable()
1367 dma_stop(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_stm32_async_rx_disable()
1369 if (data->rx_next_buffer) { in uart_stm32_async_rx_disable()
1372 .data.rx_buf.buf = data->rx_next_buffer, in uart_stm32_async_rx_disable()
1377 data->rx_next_buffer = NULL; in uart_stm32_async_rx_disable()
1378 data->rx_next_buffer_len = 0; in uart_stm32_async_rx_disable()
1381 LL_USART_EnableIT_RXNE(config->usart); in uart_stm32_async_rx_disable()
1394 struct uart_stm32_data *data = uart_dev->data; in uart_stm32_dma_tx_cb()
1401 (void)k_work_cancel_delayable(&data->dma_tx.timeout_work); in uart_stm32_dma_tx_cb()
1403 if (!dma_get_status(data->dma_tx.dma_dev, in uart_stm32_dma_tx_cb()
1404 data->dma_tx.dma_channel, &stat)) { in uart_stm32_dma_tx_cb()
1405 data->dma_tx.counter = data->dma_tx.buffer_length - in uart_stm32_dma_tx_cb()
1409 data->dma_tx.buffer_length = 0; in uart_stm32_dma_tx_cb()
1416 const struct uart_stm32_config *config = dev->config; in uart_stm32_dma_replace_buffer()
1417 struct uart_stm32_data *data = dev->data; in uart_stm32_dma_replace_buffer()
1420 LOG_DBG("Replacing RX buffer: %d", data->rx_next_buffer_len); in uart_stm32_dma_replace_buffer()
1423 data->dma_rx.offset = 0; in uart_stm32_dma_replace_buffer()
1424 data->dma_rx.counter = 0; in uart_stm32_dma_replace_buffer()
1425 data->dma_rx.buffer = data->rx_next_buffer; in uart_stm32_dma_replace_buffer()
1426 data->dma_rx.buffer_length = data->rx_next_buffer_len; in uart_stm32_dma_replace_buffer()
1427 data->dma_rx.blk_cfg.block_size = data->dma_rx.buffer_length; in uart_stm32_dma_replace_buffer()
1428 data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer; in uart_stm32_dma_replace_buffer()
1429 data->rx_next_buffer = NULL; in uart_stm32_dma_replace_buffer()
1430 data->rx_next_buffer_len = 0; in uart_stm32_dma_replace_buffer()
1432 dma_reload(data->dma_rx.dma_dev, data->dma_rx.dma_channel, in uart_stm32_dma_replace_buffer()
1433 data->dma_rx.blk_cfg.source_address, in uart_stm32_dma_replace_buffer()
1434 data->dma_rx.blk_cfg.dest_address, in uart_stm32_dma_replace_buffer()
1435 data->dma_rx.blk_cfg.block_size); in uart_stm32_dma_replace_buffer()
1437 dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_stm32_dma_replace_buffer()
1439 LL_USART_ClearFlag_IDLE(config->usart); in uart_stm32_dma_replace_buffer()
1449 struct uart_stm32_data *data = uart_dev->data; in uart_stm32_dma_rx_cb()
1456 (void)k_work_cancel_delayable(&data->dma_rx.timeout_work); in uart_stm32_dma_rx_cb()
1459 data->dma_rx.counter = data->dma_rx.buffer_length; in uart_stm32_dma_rx_cb()
1463 if (data->rx_next_buffer != NULL) { in uart_stm32_dma_rx_cb()
1478 k_work_reschedule(&data->dma_rx.timeout_work, K_TICKS(1)); in uart_stm32_dma_rx_cb()
1485 const struct uart_stm32_config *config = dev->config; in uart_stm32_async_tx()
1486 struct uart_stm32_data *data = dev->data; in uart_stm32_async_tx()
1489 if (data->dma_tx.dma_dev == NULL) { in uart_stm32_async_tx()
1490 return -ENODEV; in uart_stm32_async_tx()
1493 if (data->dma_tx.buffer_length != 0) { in uart_stm32_async_tx()
1494 return -EBUSY; in uart_stm32_async_tx()
1497 data->dma_tx.buffer = (uint8_t *)tx_data; in uart_stm32_async_tx()
1498 data->dma_tx.buffer_length = buf_size; in uart_stm32_async_tx()
1499 data->dma_tx.timeout = timeout; in uart_stm32_async_tx()
1501 LOG_DBG("tx: l=%d", data->dma_tx.buffer_length); in uart_stm32_async_tx()
1504 LL_USART_ClearFlag_TC(config->usart); in uart_stm32_async_tx()
1507 LL_USART_EnableIT_TC(config->usart); in uart_stm32_async_tx()
1510 data->dma_tx.blk_cfg.source_address = (uint32_t)data->dma_tx.buffer; in uart_stm32_async_tx()
1511 data->dma_tx.blk_cfg.block_size = data->dma_tx.buffer_length; in uart_stm32_async_tx()
1513 ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.dma_channel, in uart_stm32_async_tx()
1514 &data->dma_tx.dma_cfg); in uart_stm32_async_tx()
1518 return -EINVAL; in uart_stm32_async_tx()
1521 if (dma_start(data->dma_tx.dma_dev, data->dma_tx.dma_channel)) { in uart_stm32_async_tx()
1523 return -EFAULT; in uart_stm32_async_tx()
1527 async_timer_start(&data->dma_tx.timeout_work, data->dma_tx.timeout); in uart_stm32_async_tx()
1544 const struct uart_stm32_config *config = dev->config; in uart_stm32_async_rx_enable()
1545 struct uart_stm32_data *data = dev->data; in uart_stm32_async_rx_enable()
1548 if (data->dma_rx.dma_dev == NULL) { in uart_stm32_async_rx_enable()
1549 return -ENODEV; in uart_stm32_async_rx_enable()
1552 if (data->dma_rx.enabled) { in uart_stm32_async_rx_enable()
1554 return -EBUSY; in uart_stm32_async_rx_enable()
1557 data->dma_rx.offset = 0; in uart_stm32_async_rx_enable()
1558 data->dma_rx.buffer = rx_buf; in uart_stm32_async_rx_enable()
1559 data->dma_rx.buffer_length = buf_size; in uart_stm32_async_rx_enable()
1560 data->dma_rx.counter = 0; in uart_stm32_async_rx_enable()
1561 data->dma_rx.timeout = timeout; in uart_stm32_async_rx_enable()
1564 LL_USART_DisableIT_RXNE(config->usart); in uart_stm32_async_rx_enable()
1566 data->dma_rx.blk_cfg.block_size = buf_size; in uart_stm32_async_rx_enable()
1567 data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer; in uart_stm32_async_rx_enable()
1569 ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.dma_channel, in uart_stm32_async_rx_enable()
1570 &data->dma_rx.dma_cfg); in uart_stm32_async_rx_enable()
1574 return -EINVAL; in uart_stm32_async_rx_enable()
1577 if (dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel)) { in uart_stm32_async_rx_enable()
1579 return -EFAULT; in uart_stm32_async_rx_enable()
1588 LL_USART_ClearFlag_IDLE(config->usart); in uart_stm32_async_rx_enable()
1589 LL_USART_EnableIT_IDLE(config->usart); in uart_stm32_async_rx_enable()
1591 LL_USART_EnableIT_ERROR(config->usart); in uart_stm32_async_rx_enable()
1603 struct uart_stm32_data *data = dev->data; in uart_stm32_async_tx_abort()
1604 size_t tx_buffer_length = data->dma_tx.buffer_length; in uart_stm32_async_tx_abort()
1608 return -EFAULT; in uart_stm32_async_tx_abort()
1611 (void)k_work_cancel_delayable(&data->dma_tx.timeout_work); in uart_stm32_async_tx_abort()
1612 if (!dma_get_status(data->dma_tx.dma_dev, in uart_stm32_async_tx_abort()
1613 data->dma_tx.dma_channel, &stat)) { in uart_stm32_async_tx_abort()
1614 data->dma_tx.counter = tx_buffer_length - stat.pending_length; in uart_stm32_async_tx_abort()
1618 dma_suspend(data->dma_tx.dma_dev, data->dma_tx.dma_channel); in uart_stm32_async_tx_abort()
1620 dma_stop(data->dma_tx.dma_dev, data->dma_tx.dma_channel); in uart_stm32_async_tx_abort()
1633 const struct device *dev = data->uart_dev; in uart_stm32_async_rx_timeout()
1637 if (data->dma_rx.counter == data->dma_rx.buffer_length) { in uart_stm32_async_rx_timeout()
1651 const struct device *dev = data->uart_dev; in uart_stm32_async_tx_timeout()
1661 struct uart_stm32_data *data = dev->data; in uart_stm32_async_rx_buf_rsp()
1664 data->rx_next_buffer = buf; in uart_stm32_async_rx_buf_rsp()
1665 data->rx_next_buffer_len = len; in uart_stm32_async_rx_buf_rsp()
1672 const struct uart_stm32_config *config = dev->config; in uart_stm32_async_init()
1673 struct uart_stm32_data *data = dev->data; in uart_stm32_async_init()
1675 data->uart_dev = dev; in uart_stm32_async_init()
1677 if (data->dma_rx.dma_dev != NULL) { in uart_stm32_async_init()
1678 if (!device_is_ready(data->dma_rx.dma_dev)) { in uart_stm32_async_init()
1679 return -ENODEV; in uart_stm32_async_init()
1683 if (data->dma_tx.dma_dev != NULL) { in uart_stm32_async_init()
1684 if (!device_is_ready(data->dma_tx.dma_dev)) { in uart_stm32_async_init()
1685 return -ENODEV; in uart_stm32_async_init()
1693 k_work_init_delayable(&data->dma_rx.timeout_work, in uart_stm32_async_init()
1695 k_work_init_delayable(&data->dma_tx.timeout_work, in uart_stm32_async_init()
1699 memset(&data->dma_rx.blk_cfg, 0, sizeof(data->dma_rx.blk_cfg)); in uart_stm32_async_init()
1705 data->dma_rx.blk_cfg.source_address = in uart_stm32_async_init()
1706 LL_USART_DMA_GetRegAddr(config->usart); in uart_stm32_async_init()
1708 data->dma_rx.blk_cfg.source_address = in uart_stm32_async_init()
1709 LL_USART_DMA_GetRegAddr(config->usart, in uart_stm32_async_init()
1713 data->dma_rx.blk_cfg.dest_address = 0; /* dest not ready */ in uart_stm32_async_init()
1715 if (data->dma_rx.src_addr_increment) { in uart_stm32_async_init()
1716 data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in uart_stm32_async_init()
1718 data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in uart_stm32_async_init()
1721 if (data->dma_rx.dst_addr_increment) { in uart_stm32_async_init()
1722 data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in uart_stm32_async_init()
1724 data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in uart_stm32_async_init()
1728 data->dma_rx.blk_cfg.source_reload_en = 0; in uart_stm32_async_init()
1729 data->dma_rx.blk_cfg.dest_reload_en = 0; in uart_stm32_async_init()
1730 data->dma_rx.blk_cfg.fifo_mode_control = data->dma_rx.fifo_threshold; in uart_stm32_async_init()
1732 data->dma_rx.dma_cfg.head_block = &data->dma_rx.blk_cfg; in uart_stm32_async_init()
1733 data->dma_rx.dma_cfg.user_data = (void *)dev; in uart_stm32_async_init()
1734 data->rx_next_buffer = NULL; in uart_stm32_async_init()
1735 data->rx_next_buffer_len = 0; in uart_stm32_async_init()
1738 memset(&data->dma_tx.blk_cfg, 0, sizeof(data->dma_tx.blk_cfg)); in uart_stm32_async_init()
1744 data->dma_tx.blk_cfg.dest_address = in uart_stm32_async_init()
1745 LL_USART_DMA_GetRegAddr(config->usart); in uart_stm32_async_init()
1747 data->dma_tx.blk_cfg.dest_address = in uart_stm32_async_init()
1748 LL_USART_DMA_GetRegAddr(config->usart, in uart_stm32_async_init()
1752 data->dma_tx.blk_cfg.source_address = 0; /* not ready */ in uart_stm32_async_init()
1754 if (data->dma_tx.src_addr_increment) { in uart_stm32_async_init()
1755 data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in uart_stm32_async_init()
1757 data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in uart_stm32_async_init()
1760 if (data->dma_tx.dst_addr_increment) { in uart_stm32_async_init()
1761 data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in uart_stm32_async_init()
1763 data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in uart_stm32_async_init()
1766 data->dma_tx.blk_cfg.fifo_mode_control = data->dma_tx.fifo_threshold; in uart_stm32_async_init()
1768 data->dma_tx.dma_cfg.head_block = &data->dma_tx.blk_cfg; in uart_stm32_async_init()
1769 data->dma_tx.dma_cfg.user_data = (void *)dev; in uart_stm32_async_init()
1846 const struct uart_stm32_config *config = dev->config; in uart_stm32_clocks_enable()
1847 struct uart_stm32_data *data = dev->data; in uart_stm32_clocks_enable()
1852 if (!device_is_ready(data->clock)) { in uart_stm32_clocks_enable()
1854 return -ENODEV; in uart_stm32_clocks_enable()
1858 err = clock_control_on(data->clock, (clock_control_subsys_t)&config->pclken[0]); in uart_stm32_clocks_enable()
1864 if (IS_ENABLED(STM32_UART_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) { in uart_stm32_clocks_enable()
1866 (clock_control_subsys_t) &config->pclken[1], in uart_stm32_clocks_enable()
1879 const struct uart_stm32_config *config = dev->config; in uart_stm32_registers_configure()
1880 struct uart_stm32_data *data = dev->data; in uart_stm32_registers_configure()
1881 struct uart_config *uart_cfg = data->uart_cfg; in uart_stm32_registers_configure()
1883 LL_USART_Disable(config->usart); in uart_stm32_registers_configure()
1885 if (!device_is_ready(config->reset.dev)) { in uart_stm32_registers_configure()
1887 return -ENODEV; in uart_stm32_registers_configure()
1891 (void)reset_line_toggle_dt(&config->reset); in uart_stm32_registers_configure()
1894 LL_USART_SetTransferDirection(config->usart, in uart_stm32_registers_configure()
1897 /* Set basic parmeters, such as data-/stop-bit, parity, and baudrate */ in uart_stm32_registers_configure()
1900 /* Enable the single wire / half-duplex mode */ in uart_stm32_registers_configure()
1901 if (config->single_wire) { in uart_stm32_registers_configure()
1902 LL_USART_EnableHalfDuplex(config->usart); in uart_stm32_registers_configure()
1906 if (config->tx_rx_swap) { in uart_stm32_registers_configure()
1907 LL_USART_SetTXRXSwap(config->usart, LL_USART_TXRX_SWAPPED); in uart_stm32_registers_configure()
1912 if (config->rx_invert) { in uart_stm32_registers_configure()
1913 LL_USART_SetRXPinLevel(config->usart, LL_USART_RXPIN_LEVEL_INVERTED); in uart_stm32_registers_configure()
1918 if (config->tx_invert) { in uart_stm32_registers_configure()
1919 LL_USART_SetTXPinLevel(config->usart, LL_USART_TXPIN_LEVEL_INVERTED); in uart_stm32_registers_configure()
1924 if (config->de_enable) { in uart_stm32_registers_configure()
1925 if (!IS_UART_DRIVER_ENABLE_INSTANCE(config->usart)) { in uart_stm32_registers_configure()
1926 LOG_ERR("%s does not support driver enable", dev->name); in uart_stm32_registers_configure()
1927 return -EINVAL; in uart_stm32_registers_configure()
1931 LL_USART_SetDEAssertionTime(config->usart, config->de_assert_time); in uart_stm32_registers_configure()
1932 LL_USART_SetDEDeassertionTime(config->usart, config->de_deassert_time); in uart_stm32_registers_configure()
1934 if (config->de_invert) { in uart_stm32_registers_configure()
1935 LL_USART_SetDESignalPolarity(config->usart, LL_USART_DE_POLARITY_LOW); in uart_stm32_registers_configure()
1940 LL_USART_Enable(config->usart); in uart_stm32_registers_configure()
1944 while (!(LL_USART_IsActiveFlag_TEACK(config->usart))) { in uart_stm32_registers_configure()
1950 while (!(LL_USART_IsActiveFlag_REACK(config->usart))) { in uart_stm32_registers_configure()
1969 const struct uart_stm32_config *config = dev->config; in uart_stm32_init()
1978 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in uart_stm32_init()
1991 config->irq_config_func(dev); in uart_stm32_init()
1995 if (config->wakeup_source) { in uart_stm32_init()
1996 /* Enable ability to wakeup device in Stop mode in uart_stm32_init()
2001 LL_USART_EnableInStopMode(config->usart); in uart_stm32_init()
2002 if (config->wakeup_line != STM32_EXTI_LINE_NONE) { in uart_stm32_init()
2003 /* Prepare the WAKEUP with the expected EXTI line */ in uart_stm32_init()
2004 LL_EXTI_EnableIT_0_31(BIT(config->wakeup_line)); in uart_stm32_init()
2019 const struct uart_stm32_config *config = dev->config; in uart_stm32_suspend_setup()
2022 /* Make sure that no USART transfer is on-going */ in uart_stm32_suspend_setup()
2023 while (LL_USART_IsActiveFlag_BUSY(config->usart) == 1) { in uart_stm32_suspend_setup()
2026 while (LL_USART_IsActiveFlag_TC(config->usart) == 0) { in uart_stm32_suspend_setup()
2030 while (LL_USART_IsActiveFlag_REACK(config->usart) == 0) { in uart_stm32_suspend_setup()
2034 LL_USART_ClearFlag_ORE(config->usart); in uart_stm32_suspend_setup()
2040 const struct uart_stm32_config *config = dev->config; in uart_stm32_pm_action()
2041 struct uart_stm32_data *data = dev->data; in uart_stm32_pm_action()
2048 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in uart_stm32_pm_action()
2054 err = clock_control_on(data->clock, (clock_control_subsys_t)&config->pclken[0]); in uart_stm32_pm_action()
2063 err = clock_control_off(data->clock, (clock_control_subsys_t)&config->pclken[0]); in uart_stm32_pm_action()
2070 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP); in uart_stm32_pm_action()
2071 if ((err < 0) && (err != -ENOENT)) { in uart_stm32_pm_action()
2073 * If returning -ENOENT, no pins where defined for sleep mode : in uart_stm32_pm_action()
2083 return -ENOTSUP; in uart_stm32_pm_action()