4  * SPDX-License-Identifier: Apache-2.0
38 /* Pin-control local functions for peripheral devices */
39 static bool npcx_periph_pinmux_has_lock(int group)  in npcx_periph_pinmux_has_lock()  argument
42 	if (group == 0x00 || (group >= 0x02 && group <= 0x04) || group == 0x06 ||  in npcx_periph_pinmux_has_lock()
43 		group == 0x0b || group == 0x0f) {  in npcx_periph_pinmux_has_lock()
47 	if (group == 0x00 || (group >= 0x02 && group <= 0x06) || group == 0x0b ||  in npcx_periph_pinmux_has_lock()
48 		group == 0x0d || (group >= 0x0f && group <= 0x12)) {  in npcx_periph_pinmux_has_lock()
59 	uint8_t alt_mask = BIT(alt->bit);  in npcx_periph_pinmux_configure()
62 	 * is_alternate == 0 means select GPIO, otherwise Alternate Func.  in npcx_periph_pinmux_configure()
68 	if (is_alternate != alt->inverted) {  in npcx_periph_pinmux_configure()
69 		NPCX_DEVALT(scfg_base, alt->group) |=  alt_mask;  in npcx_periph_pinmux_configure()
71 		NPCX_DEVALT(scfg_base, alt->group) &= ~alt_mask;  in npcx_periph_pinmux_configure()
74 	if (is_locked && npcx_periph_pinmux_has_lock(alt->group)) {  in npcx_periph_pinmux_configure()
75 		NPCX_DEVALT_LK(scfg_base, alt->group) |= alt_mask;  in npcx_periph_pinmux_configure()
85 		NPCX_PUPD_EN(scfg_base, pupd->group) &= ~BIT(pupd->bit);  in npcx_periph_pupd_configure()
87 		NPCX_PUPD_EN(scfg_base, pupd->group) |=  BIT(pupd->bit);  in npcx_periph_pupd_configure()
96 	/* Find selected pwm module which enables open-drain prop. */  in npcx_periph_pwm_drive_mode_configure()
98 		if (periph->group == pwm_pinctrl_cfg[i].channel) {  in npcx_periph_pwm_drive_mode_configure()
111 		inst->PWMCTLEX |= BIT(NPCX_PWMCTLEX_OD_OUT);  in npcx_periph_pwm_drive_mode_configure()
113 		inst->PWMCTLEX &= ~BIT(NPCX_PWMCTLEX_OD_OUT);  in npcx_periph_pwm_drive_mode_configure()
119 	if (pin->cfg.periph.type == NPCX_PINCTRL_TYPE_PERIPH_PINMUX) {  in npcx_periph_configure()
121 		npcx_periph_pinmux_configure(&pin->cfg.periph,  in npcx_periph_configure()
122 					     !pin->flags.pinmux_gpio,  in npcx_periph_configure()
123 					     pin->flags.pinmux_lock);  in npcx_periph_configure()
124 	} else if (pin->cfg.periph.type == NPCX_PINCTRL_TYPE_PERIPH_PUPD) {  in npcx_periph_configure()
126 		npcx_periph_pupd_configure(&pin->cfg.periph,  in npcx_periph_configure()
127 			pin->flags.io_bias_type);  in npcx_periph_configure()
128 	} else if (pin->cfg.periph.type == NPCX_PINCTRL_TYPE_PERIPH_DRIVE) {  in npcx_periph_configure()
130 		npcx_periph_pwm_drive_mode_configure(&pin->cfg.periph,  in npcx_periph_configure()
131 			pin->flags.io_drive_type == NPCX_DRIVE_TYPE_OPEN_DRAIN);  in npcx_periph_configure()
139 	const struct npcx_psl_input *psl_in = (const struct npcx_psl_input *)&pin->cfg.psl_in;  in npcx_psl_input_detection_configure()
142 	if (pin->flags.psl_in_polarity == NPCX_PSL_IN_POL_HIGH) {  in npcx_psl_input_detection_configure()
143 		NPCX_DEVALT(scfg_base, psl_in->pol_group) |=  BIT(psl_in->pol_bit);  in npcx_psl_input_detection_configure()
145 		NPCX_DEVALT(scfg_base, psl_in->pol_group) &= ~BIT(psl_in->pol_bit);  in npcx_psl_input_detection_configure()
149 	if (pin->flags.psl_in_mode == NPCX_PSL_IN_MODE_EDGE) {  in npcx_psl_input_detection_configure()
150 		inst_glue->PSL_CTS |= NPCX_PSL_CTS_MODE_BIT(psl_in->port);  in npcx_psl_input_detection_configure()
152 		inst_glue->PSL_CTS &= ~NPCX_PSL_CTS_MODE_BIT(psl_in->port);  in npcx_psl_input_detection_configure()
158 	const struct npcx_dev_ctl *ctrl = (const struct npcx_dev_ctl *)&pin->cfg.dev_ctl;  in npcx_device_control_configure()
161 	SET_FIELD(NPCX_DEV_CTL(scfg_base, ctrl->offest),  in npcx_device_control_configure()
162 			      FIELD(ctrl->field_offset, ctrl->field_size),  in npcx_device_control_configure()
163 			      ctrl->field_value);  in npcx_device_control_configure()
184 			return -ENOTSUP;  in pinctrl_configure_pins()