1 /* ieee802154_mcr20a.c - NXP MCR20A driver */
8  * SPDX-License-Identifier: Apache-2.0
41  * max. TX duration = (PR + SFD + FLI + PDU + FCS)
113 #define MCR20A_OUTPUT_POWER_MIN	(-35)
132  * Fc = 2405 + 5(k - 11) , k = 11,12,...,26
157 	const struct mcr20a_config *config = dev->config;  in z_mcr20a_read_reg()
178 	if (spi_transceive_dt(&config->bus, &tx, &rx) == 0) {  in z_mcr20a_read_reg()
179 		return cmd_buf[len - 1];  in z_mcr20a_read_reg()
191 	const struct mcr20a_config *config = dev->config;  in z_mcr20a_write_reg()
207 	return (spi_write_dt(&config->bus, &tx) == 0);  in z_mcr20a_write_reg()
214 	const struct mcr20a_config *config = dev->config;  in z_mcr20a_write_burst()
235 	return (spi_write_dt(&config->bus, &tx) == 0);  in z_mcr20a_write_burst()
242 	const struct mcr20a_config *config = dev->config;  in z_mcr20a_read_burst()
267 	return (spi_transceive_dt(&config->bus, &tx, &rx) == 0);  in z_mcr20a_read_burst()
327 	return -EIO;  in mcr20a_timer_set()
355 	return -EIO;  in mcr20a_timer_init()
387 	return -EIO;  in mcr20a_t4cmp_set()
412 	return -EIO;  in mcr20a_t4cmp_clear()
422 		retries--;  in xcvseq_wait_until_idle()
441 			return -1;  in mcr20a_abort_sequence()
448 		return -1;  in mcr20a_abort_sequence()
455 		return -1;  in mcr20a_abort_sequence()
480 		return -EIO;  in mcr20a_set_sequence()
486 #define DIV_ROUND_CLOSEST_WITH_OPPOSITE_SIGNS(n, d) (((n) - (d)/2)/(d))
499 	 * The second is derived from empiric values (see Figure 3-10)  in mcr20a_get_rssi()
510 	int16_t numerator = ((int16_t)100 * lqi) - 29540; /* always negative */  in mcr20a_get_rssi()
517 	struct mcr20a_context *mcr20a = dev->data;  in get_mac()
518 	uint32_t *ptr = (uint32_t *)(mcr20a->mac_addr);  in get_mac()
521 	ptr = (uint32_t *)(mcr20a->mac_addr + 4);  in get_mac()
524 	mcr20a->mac_addr[0] = (mcr20a->mac_addr[0] & ~0x01) | 0x02;  in get_mac()
526 	return mcr20a->mac_addr;  in get_mac()
532 	const struct mcr20a_config *config = dev->config;  in read_rxfifo_content()
540 			.buf = buf->data,  in read_rxfifo_content()
553 	if (spi_transceive_dt(&config->bus, &tx, &rx) != 0) {  in read_rxfifo_content()
564 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_rx()
570 	pkt_len = len - MCR20A_FCS_LENGTH;  in mcr20a_rx()
572 	pkt = net_pkt_rx_alloc_with_buffer(mcr20a->iface, pkt_len,  in mcr20a_rx()
579 	if (!read_rxfifo_content(dev, pkt->buffer, pkt_len)) {  in mcr20a_rx()
585 	if (ieee802154_handle_ack(mcr20a->iface, pkt) == NET_OK) {  in mcr20a_rx()
598 	if (net_recv_data(mcr20a->iface, pkt) < 0) {  in mcr20a_rx()
603 	log_stack_usage(&mcr20a->mcr20a_rx_thread);  in mcr20a_rx()
620 	struct mcr20a_context *mcr20a = dev->data;  in irqsts1_event()
643 				atomic_set(&mcr20a->seq_retval, -EBUSY);  in irqsts1_event()
650 			atomic_set(&mcr20a->seq_retval, 0);  in irqsts1_event()
672 				atomic_set(&mcr20a->seq_retval, -EBUSY);  in irqsts1_event()
681 				atomic_set(&mcr20a->seq_retval, 0);  in irqsts1_event()
708 	struct mcr20a_context *mcr20a = dev->data;  in irqsts3_event()
717 		atomic_set(&mcr20a->seq_retval, -EBUSY);  in irqsts3_event()
736 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_thread_main()
742 		k_sem_take(&mcr20a->isr_sem, K_FOREVER);  in mcr20a_thread_main()
744 		k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);  in mcr20a_thread_main()
800 		k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_thread_main()
803 			k_sem_give(&mcr20a->seq_sync);  in mcr20a_thread_main()
814 	k_sem_give(&mcr20a->isr_sem);  in irqb_int_handler()
820 	const struct mcr20a_config *config = dev->config;  in enable_irqb_interrupt()
825 	gpio_pin_interrupt_configure_dt(&config->irq_gpio, flags);  in enable_irqb_interrupt()
830 	const struct mcr20a_config *config = dev->config;  in setup_gpio_callbacks()
831 	struct mcr20a_context *mcr20a = dev->data;  in setup_gpio_callbacks()
833 	gpio_init_callback(&mcr20a->irqb_cb,  in setup_gpio_callbacks()
835 			   BIT(config->irq_gpio.pin));  in setup_gpio_callbacks()
836 	gpio_add_callback(config->irq_gpio.port, &mcr20a->irqb_cb);  in setup_gpio_callbacks()
849 		return -EIO;  in mcr20a_set_cca_mode()
864 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_cca()
867 	k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);  in mcr20a_cca()
874 	k_sem_init(&mcr20a->seq_sync, 0, 1);  in mcr20a_cca()
893 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_cca()
894 	retval = k_sem_take(&mcr20a->seq_sync,  in mcr20a_cca()
903 	return mcr20a->seq_retval;  in mcr20a_cca()
906 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_cca()
907 	return -EIO;  in mcr20a_cca()
912 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_set_channel()
915 	int retval = -EIO;  in mcr20a_set_channel()
919 		return channel < 11 ? -ENOTSUP : -EINVAL;  in mcr20a_set_channel()
922 	k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);  in mcr20a_set_channel()
937 	channel -= 11U;  in mcr20a_set_channel()
957 		retval = -EIO;  in mcr20a_set_channel()
960 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_set_channel()
967 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_set_pan_id()
970 	k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);  in mcr20a_set_pan_id()
974 		k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_set_pan_id()
975 		return -EIO;  in mcr20a_set_pan_id()
978 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_set_pan_id()
987 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_set_short_addr()
990 	k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);  in mcr20a_set_short_addr()
994 		k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_set_short_addr()
995 		return -EIO;  in mcr20a_set_short_addr()
998 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_set_short_addr()
1007 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_set_ieee_addr()
1009 	k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);  in mcr20a_set_ieee_addr()
1013 		k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_set_ieee_addr()
1014 		return -EIO;  in mcr20a_set_ieee_addr()
1017 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_set_ieee_addr()
1033 		return -ENOTSUP;  in mcr20a_filter()
1037 		return mcr20a_set_ieee_addr(dev, filter->ieee_addr);  in mcr20a_filter()
1039 		return mcr20a_set_short_addr(dev, filter->short_addr);  in mcr20a_filter()
1041 		return mcr20a_set_pan_id(dev, filter->pan_id);  in mcr20a_filter()
1044 	return -ENOTSUP;  in mcr20a_filter()
1049 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_set_txpower()
1052 	k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);  in mcr20a_set_txpower()
1060 	pwr = pow_lt[dbm - MCR20A_OUTPUT_POWER_MIN];  in mcr20a_set_txpower()
1065 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_set_txpower()
1069 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_set_txpower()
1071 	return -EIO;  in mcr20a_set_txpower()
1078 	const struct mcr20a_config *config = dev->config;  in write_txfifo_content()
1079 	size_t payload_len = frag->len;  in write_txfifo_content()
1090 			.buf = frag->data,  in write_txfifo_content()
1104 	return (spi_write_dt(&config->bus, &tx) == 0);  in write_txfifo_content()
1112 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_tx()
1119 		return -ENOTSUP;  in mcr20a_tx()
1122 	k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);  in mcr20a_tx()
1124 	LOG_DBG("%p (%u)", frag, frag->len);  in mcr20a_tx()
1141 	k_sem_init(&mcr20a->seq_sync, 0, 1);  in mcr20a_tx()
1153 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_tx()
1154 	retval = k_sem_take(&mcr20a->seq_sync,  in mcr20a_tx()
1163 	return mcr20a->seq_retval;  in mcr20a_tx()
1166 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_tx()
1167 	return -EIO;  in mcr20a_tx()
1172 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_start()
1176 	k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);  in mcr20a_start()
1186 		timeout--;  in mcr20a_start()
1218 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_start()
1224 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_start()
1225 	return -EIO;  in mcr20a_start()
1230 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_stop()
1233 	k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);  in mcr20a_stop()
1258 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_stop()
1263 	k_mutex_unlock(&mcr20a->phy_mutex);  in mcr20a_stop()
1265 	return -EIO;  in mcr20a_stop()
1268 /* driver-allocated attribute memory - constant across all driver instances */
1302 	return -EIO;  in mcr20a_update_overwrites()
1307 	const struct mcr20a_config *config = dev->config;  in power_on_and_setup()
1313 		gpio_pin_set_dt(&config->reset_gpio, 1);  in power_on_and_setup()
1315 		gpio_pin_set_dt(&config->reset_gpio, 0);  in power_on_and_setup()
1319 			timeout--;  in power_on_and_setup()
1320 			pin = gpio_pin_get_dt(&config->irq_gpio);  in power_on_and_setup()
1325 			return -EIO;  in power_on_and_setup()
1335 		return -EIO;  in power_on_and_setup()
1358 	/* Enable Sequence-end interrupt */  in power_on_and_setup()
1370 	const struct mcr20a_config *config = dev->config;  in configure_gpios()
1373 	if (!gpio_is_ready_dt(&config->irq_gpio)) {  in configure_gpios()
1375 		return -ENODEV;  in configure_gpios()
1378 	gpio_pin_configure_dt(&config->irq_gpio, GPIO_INPUT);  in configure_gpios()
1382 		if (!gpio_is_ready_dt(&config->reset_gpio)) {  in configure_gpios()
1384 			return -EINVAL;  in configure_gpios()
1387 		gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_ACTIVE);  in configure_gpios()
1395 	const struct mcr20a_config *config = dev->config;  in mcr20a_init()
1396 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_init()
1398 	k_mutex_init(&mcr20a->phy_mutex);  in mcr20a_init()
1399 	k_sem_init(&mcr20a->isr_sem, 0, 1);  in mcr20a_init()
1404 		LOG_ERR("Configuring GPIOS failed");  in mcr20a_init()
1405 		return -EIO;  in mcr20a_init()
1408 	if (!spi_is_ready_dt(&config->bus)) {  in mcr20a_init()
1410 		return -EIO;  in mcr20a_init()
1417 		return -EIO;  in mcr20a_init()
1420 	k_thread_create(&mcr20a->mcr20a_rx_thread, mcr20a->mcr20a_rx_stack,  in mcr20a_init()
1424 	k_thread_name_set(&mcr20a->mcr20a_rx_thread, "mcr20a_rx");  in mcr20a_init()
1432 	struct mcr20a_context *mcr20a = dev->data;  in mcr20a_iface_init()
1437 	mcr20a->iface = iface;  in mcr20a_iface_init()