Lines Matching +full:40 +full:mhz

126 /* System Time Counter (40-bit) */
129 /* Note 40 bit register */
136 /* Note 40 bit register */
170 /* Transmit Pulse Repetition Frequency = 4 Mhz */
172 /* Transmit Pulse Repetition Frequency = 16 Mhz */
174 /* Transmit Pulse Repetition Frequency = 64 Mhz */
212 /* Delayed Send or Receive Time (40-bit) */
328 /* Note 40 bit register */
557 /* Note 40 bit register */
577 /* read only 5 bytes (the adjusted timestamp (40:0)) */
580 /* byte 0..4 40 bit Reports the fully adjusted time of reception. */
586 /* byte 9..13 40 bit Raw Timestamp for the frame */
594 /* 40-bits = 5 bytes */
597 /* byte 0..4 40 bit Reports the fully adjusted time of transmission */
599 /* byte 5..9 40 bit Raw Timestamp for the frame */
749  *		    00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz.
757  *		    00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz.
762  *		    00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz.
767  *		    00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz.
1752  * The system clock will run off the 19.2 MHz XTI clock until the PLL is
1753  * calibrated and locked, then it will switch over the 125 MHz PLL clock
1756 /* Force system clock to be the 19.2 MHz XTI clock. */
1758 /* Force system clock to the 125 MHz PLL clock. */
1762 /* Force RX clock enable and sourced clock from the 19.2 MHz XTI clock */
1764 /* Force RX clock enable and sourced from the 125 MHz PLL clock */
1770 /* Force TX clock enable and sourced clock from the 19.2 MHz XTI clock */
1772 /* Force TX clock enable and sourced from the 125 MHz PLL clock */
1918 /* Defaults from Table 40: Sub-Register 0x2A:0B – TC_PGDELAY */
1931  *     Transmit Power Control values for 16 MHz, with DIS_STXP = 0
1945  *     Transmit Power Control values for 64 MHz, with DIS_STXP = 0
1959  *     Transmit Power Control values for 16 MHz, with DIS_STXP = 1
1973  *     Transmit Power Control values for 64 MHz, with DIS_STXP = 1