2  * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4  * SPDX-License-Identifier: Apache-2.0
25 /* sifive GPIO register-set structure */
50 	/* multi-level encoded interrupt corresponding to pin 0 */
64 	((const struct gpio_sifive_config * const)(dev)->config)
66 	((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
68 	((struct gpio_sifive_data *)(dev)->data)
97 	return (plic_irq - base_irq);  in gpio_sifive_plic_to_pin()
107 	uint8_t pin = 1 + (riscv_plic_get_irq() -  in gpio_sifive_irq_handler()
108 			   (uint8_t)(cfg->gpio_irq_base >> CONFIG_1ST_LEVEL_INTERRUPT_BITS));  in gpio_sifive_irq_handler()
115 	 * It is certainly possible, especially on double-edge, that  in gpio_sifive_irq_handler()
120 	 * Clear all the conditions so we only invoke the callback  in gpio_sifive_irq_handler()
123 	gpio->rise_ip = BIT(pin);  in gpio_sifive_irq_handler()
124 	gpio->fall_ip = BIT(pin);  in gpio_sifive_irq_handler()
125 	gpio->high_ip = BIT(pin);  in gpio_sifive_irq_handler()
126 	gpio->low_ip = BIT(pin);  in gpio_sifive_irq_handler()
129 	gpio_fire_callbacks(&data->cb, dev, BIT(pin));  in gpio_sifive_irq_handler()
148 		return -EINVAL;  in gpio_sifive_config()
151 	/* We cannot support open-source open-drain configuration */  in gpio_sifive_config()
153 		return -ENOTSUP;  in gpio_sifive_config()
156 	/* We only support pull-ups, not pull-downs */  in gpio_sifive_config()
158 		return -ENOTSUP;  in gpio_sifive_config()
161 	/* Set pull-up if requested */  in gpio_sifive_config()
162 	WRITE_BIT(gpio->pue, pin, flags & GPIO_PULL_UP);  in gpio_sifive_config()
168 		gpio->out_val |= BIT(pin);  in gpio_sifive_config()
171 		gpio->out_val &= ~BIT(pin);  in gpio_sifive_config()
175 	WRITE_BIT(gpio->out_en, pin, flags & GPIO_OUTPUT);  in gpio_sifive_config()
176 	WRITE_BIT(gpio->in_en, pin, flags & GPIO_INPUT);  in gpio_sifive_config()
186 	*value = gpio->in_val;  in gpio_sifive_port_get_raw()
197 	gpio->out_val = (gpio->out_val & ~mask) | (value & mask);  in gpio_sifive_port_set_masked_raw()
207 	gpio->out_val |= mask;  in gpio_sifive_port_set_bits_raw()
217 	gpio->out_val &= ~mask;  in gpio_sifive_port_clear_bits_raw()
227 	gpio->out_val ^= mask;  in gpio_sifive_port_toggle_bits()
240 	gpio->rise_ie &= ~BIT(pin);  in gpio_sifive_pin_interrupt_configure()
241 	gpio->fall_ie &= ~BIT(pin);  in gpio_sifive_pin_interrupt_configure()
242 	gpio->high_ie &= ~BIT(pin);  in gpio_sifive_pin_interrupt_configure()
243 	gpio->low_ie  &= ~BIT(pin);  in gpio_sifive_pin_interrupt_configure()
247 		irq_disable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin));  in gpio_sifive_pin_interrupt_configure()
252 			gpio->high_ip = BIT(pin);  in gpio_sifive_pin_interrupt_configure()
253 			gpio->high_ie |= BIT(pin);  in gpio_sifive_pin_interrupt_configure()
256 			gpio->low_ip = BIT(pin);  in gpio_sifive_pin_interrupt_configure()
257 			gpio->low_ie  |= BIT(pin);  in gpio_sifive_pin_interrupt_configure()
259 		irq_enable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin));  in gpio_sifive_pin_interrupt_configure()
266 			gpio->rise_ip = BIT(pin);  in gpio_sifive_pin_interrupt_configure()
267 			gpio->rise_ie |= BIT(pin);  in gpio_sifive_pin_interrupt_configure()
270 			gpio->fall_ip = BIT(pin);  in gpio_sifive_pin_interrupt_configure()
271 			gpio->fall_ie |= BIT(pin);  in gpio_sifive_pin_interrupt_configure()
273 		irq_enable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin));  in gpio_sifive_pin_interrupt_configure()
277 		return -ENOTSUP;  in gpio_sifive_pin_interrupt_configure()
289 	return gpio_manage_callback(&data->cb, callback, set);  in gpio_sifive_manage_callback()
294 				    gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)  in gpio_sifive_port_get_dir()  argument
298 	map &= cfg->common.port_pin_mask;  in gpio_sifive_port_get_dir()
301 		*inputs = map & DEV_GPIO(dev)->in_en;  in gpio_sifive_port_get_dir()
304 	if (outputs != NULL) {  in gpio_sifive_port_get_dir()
305 		*outputs = map & DEV_GPIO(dev)->out_en;  in gpio_sifive_port_get_dir()
340 	/* Ensure that all gpio registers are reset to 0 initially */  in gpio_sifive_init()
341 	gpio->in_en   = 0U;  in gpio_sifive_init()
342 	gpio->out_en  = 0U;  in gpio_sifive_init()
343 	gpio->pue     = 0U;  in gpio_sifive_init()
344 	gpio->rise_ie = 0U;  in gpio_sifive_init()
345 	gpio->fall_ie = 0U;  in gpio_sifive_init()
346 	gpio->high_ie = 0U;  in gpio_sifive_init()
347 	gpio->low_ie  = 0U;  in gpio_sifive_init()
348 	gpio->iof_en  = 0U;  in gpio_sifive_init()
349 	gpio->iof_sel = 0U;  in gpio_sifive_init()
350 	gpio->invert  = 0U;  in gpio_sifive_init()
353 	cfg->gpio_cfg_func();  in gpio_sifive_init()